Memory devices having source lines directly coupled to body regions and methods
US-2024386966-A1 · Nov 21, 2024 · US
Extended select gate lifetime
US8929151B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8929151-B2 |
| Application number | US-201414313155-A |
| Country | US |
| Kind code | B2 |
| Filing date | Jun 24, 2014 |
| Priority date | Jun 21, 2012 |
| Publication date | Jan 6, 2015 |
| Grant date | Jan 6, 2015 |
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Abstract
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A flash memory device may include two or more flash memory cells organized as a NAND string in a block of flash memory cells, and flash cells, coupled to the NAND string at opposite ends, to function as select gates. The flash memory device may be capable of providing information related to a voltage threshold of the select gates to a flash controller, erasing the flash cells that function as select gates in response to a select gate erase command, and programming the flash cells that function as select gates in response to a select gate program command. A flash controller may be coupled to the flash memory device, and is capable of sending the select gate erase commend to the flash memory device if the information provided by the flash memory device indicates that the voltage threshold of at least one of the select gates is above a predetermined voltage level, and sending the select gate program command to the flash memory device if the information provided by the flash memory device indicates that the voltage threshold of at least one of the select gates is outside of a predetermined voltage range.
First claim
Opening claim text (preview).
What is claimed is: 1. A method to manage a memory device comprising: sending a select gate erase command to a memory device to erase select gates in a block of the memory device if an indication that a voltage threshold of the select gates is above a predetermined voltage level is received; sending a select gate program command to the memory device to program the select gates in the block of the memory device if a first indication that the voltage threshold of the select gates…
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- G11C16/14Primary
Physics · mapped topic
Physics · mapped topic
Physics · mapped topic
Physics · mapped topic
Physics · mapped topic
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- What does patent US8929151B2 cover?
- A flash memory device may include two or more flash memory cells organized as a NAND string in a block of flash memory cells, and flash cells, coupled to the NAND string at opposite ends, to function as select gates. The flash memory device may be capable of providing information related to a voltage threshold of the select gates to a flash controller, erasing the flash cells that function as s…
- Who is the assignee on this patent?
- Wakchaure Yogesh, Pangal Kiran, Guo Xin, and 3 more
- What technology area does this patent fall under?
- Primary CPC classification G11C16/14. Mapped technology areas include Physics.
- When was this patent published?
- Publication date Tue Jan 06 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).