Through printed circuit board (PCB) vias

Patent metadata

Field	Value
Publication number	US-9408304-B2
Application number	US-201414161228-A
Country	US
Kind code	B2
Filing date	Jan 22, 2014
Priority date	Jan 22, 2014
Publication date	Aug 2, 2016
Grant date	Aug 2, 2016

Abstract

A broadband through printed circuit board (PCB) for millimeter wave application and methods of manufacture are disclosed. The structure includes a multiple layered body and an opening in the multiple layered body. The structure further includes at least one signal via extending through the opening. The structure further includes ground vias extending through the opening and on opposing sides of the at least one signal via. The structure further includes a ground plate above and below the opening and electrically connected to the ground vias at respective ends. The structure further includes a microstrip signal via above and below the opening and electrically connected to the at least one signal via.

First claim

What is claimed is:

1. A structure, comprising:
a multiple layered body;
an opening in the multiple layered body;
at least one signal via extending through the opening;
ground vias extending through the opening and on opposing sides of the at least one signal via;
a ground plate above and below the opening and electrically connected to the ground vias at respective ends; and
a microstrip signal line above and below the opening and electrically connected to the at least one signal via.

2. The structure of claim 1 , wherein the multiple layered body comprises alternating conductive layers and insulating layers.

3. The structure of claim 2 , wherein:
the conductive layers are copper or copper alloy; and
a top layer and a bottom layer of the conductive layers are clad in at least one of nickel and gold.

4. The structure of claim 3 , wherein the top layer and the bottom layer of the conductive layers has a thickness less than remaining layers of the conductive layers.

5. The structure of claim 1 , wherein the ground plate and the microstrip signal line are on different levels.

6. The structure of claim 1 , wherein the at least one signal via is two signal vias and the ground vias are provided on opposing sides of the two signal vias.

7. The structure of claim 6 , wherein the ground vias are two ground vias.

8. The structure of claim 1 , further comprising secondary ground vias provided within holes of the multiple layers and which are symmetrically arranged about the opening.

9. The structure of claim 8 , wherein the secondary ground vias comprise self-contained ground shields.

10. The structure of claim 9 , wherein the ground vias and the at least one signal via are spaced apart from each other.

11. The structure of claim 10 , wherein:
the at least one signal via is two signal vias spaced apart from one another; and
the ground vias is two ground vias.

12. The structure of claim 1 , wherein the ground plates partially surround the at least one signal via.

13. A direct wafer probing device, comprising:
a board;
contacts at a bottom of the board;
one or more broadband through conductive vias contacting the contacts at the bottom of the board; and
one or more coaxial connectors on a top of the board, connecting to the one or more broadband through conductive vias.

14. The structure of claim 13 , wherein the one or more broadband through conductive vias comprise at least one signal via and two ground vias each of which are on opposing sides of the at least one signal via.

15. The structure of claim 14 , wherein the at least one signal via is two signal vias and the two ground vias and two signal vias are configured as a ground-signal-signal-ground.

16. A method of forming a board, comprising:
determining a thickness of a board based on application requirements;
determining via diameter and via pad diameter based on board design constraints;
determining a width of a launch trace which forms a microstrip signal line;
determining an initial distance between a signal via and two dominant ground vias for a required impedance; and
determining an initial clearance size of return grounds for the signal via and an opening size on ground/power planes by a minimum spacing.

17. The method of claim 16 , further comprising checking a performance of the signal via from top to bottom and, if the performance is not met, then repeating steps of claim 16 to modify clearance size and/or opening size and/or line spacing.

18. The method of claim 16 , wherein the determining the thickness of the board comprises determining a number of material layers use in the board.

19. The method of claim 16 , wherein the thickness of the board is about 100-130 mil, in order to withstand stresses of testing.

20. The method of claim 16 , wherein the via diameter and via pad diameter are a minimum via size and pad size.

Assignees

• IBM
• Globalfoundries Inc

Inventors

• Brown Dana H
• Ding Hanyi
• Ding Yan
• Ferrario John S

Classifications

• Y10T29/49004

  including measuring or testing of device or component part · CPC title

• H05K1/09

  Use of materials for the {conductive, e.g. } metallic pattern · CPC title

• H05K1/115 Primary

  Via connections; Lands around holes or via connections (H05K1/112 takes precedence) · CPC title

• H05K1/0298

  Multilayer circuits · CPC title

• H05K3/4697 Primary

  having cavities, e.g. for mounting components (H05K3/4691 takes precedence) · CPC title