Power converter package including top-drain configured power FET

Patent metadata

Field	Value
Publication number	US-9397212-B2
Application number	US-201314021802-A
Country	US
Kind code	B2
Filing date	Sep 9, 2013
Priority date	Oct 18, 2012
Publication date	Jul 19, 2016
Grant date	Jul 19, 2016

Abstract

In one implementation, a semiconductor package includes a top-drain vertical FET in a first active die, a source of the top-drain vertical FET situated on a source side of the first active die and a drain and a gate of the top-drain vertical FET situated on a drain side of the first active die. The semiconductor package also includes a bottom-drain vertical FET in a second active die, a source and a gate of the bottom-drain vertical FET situated on a source side of the second active die and a drain of the bottom-drain vertical FET situated on a drain side of the second active die. The semiconductor package includes a conductive carrier attached to the source side of the first active die and to the drain side of the second active die, the conductive carrier coupling the source of the top-drain vertical FET to the drain of the bottom-drain vertical FET.

First claim

The invention claimed is:

1. A semiconductor package comprising:
a top-drain vertical FET in a first active die, a source of said top-drain vertical FET situated on a source side of said first active die and a drain and a gate of said top-drain vertical FET situated on a drain side of said first active die;
a bottom-drain vertical FET in a second active die, a source and a gate of said bottom-drain vertical FET situated on a source side of said second active die and a drain of said bottom-drain vertical FET situated on a drain side of said second active die;
a conductive carrier attached to said source side of said first active die and to said drain side of said second active die;
said conductive carrier coupling said source of said top-drain vertical FET to said drain of said bottom-drain vertical FET; and
a patterned dielectric formed over said drain side of said first active die and said source side of said second active die, said patterned dielectric exposing said drain and said gate of said top-drain vertical FET and said source and said gate of said bottom-drain vertical FET.

2. The semiconductor package of claim 1 , wherein said conductive carrier comprises a lead frame.

3. The semiconductor package of claim 1 , wherein said top-drain vertical FET and said bottom-drain vertical FET comprise silicon FETs.

4. The semiconductor package of claim 1 , wherein said top-drain vertical FET and said bottom-drain vertical FET comprise III-Nitride FETs.

5. The semiconductor package of claim 1 , further comprising a driver integrated circuit (IC) for driving at least one of said top-drain vertical FET and said bottom-drain vertical FET.

6. The semiconductor package of claim 1 , further comprising a driver IC for driving at least one of said top-drain vertical FET and said bottom-drain vertical FET, said conductive carrier being attached to said driver IC.

7. The semiconductor package of claim 1 , wherein said top-drain vertical FET and said bottom-drain vertical FET are utilized to implement a switching stage of a buck converter.

8. A semiconductor package comprising:
a power converter switching stage including a control vertical PET in a control active die and a sync vertical FET in a sync active die;
said control vertical FET having a source situated on a source side of said control active die and a drain and a gate situated on a drain side of said control active die;
said sync vertical FET having a source and a gate situated on a source side of said sync active die and a drain situated on a drain side of said sync active die;
a conductive carrier being attached to said source side of said control active die and to said drain side of said sync active die;
said conductive carrier providing a switch node of said power converter switching stage; and
a patterned dielectric formed over said drain side of said control active die and said source side of said sync active die, said patterned dielectric exposing said drain and said gate of said control vertical FET and said source and said gate of said sync vertical FET.

9. The semiconductor package of claim 8 , wherein said conductive carrier comprises a lead frame.

10. The semiconductor package of claim 8 , wherein said control vertical FET and said sync vertical FET comprise silicon FETs.

11. The semiconductor package of claim 8 , wherein said control vertical FET and said sync vertical FET comprise III-Nitride FETs.

12. The semiconductor package of claim 8 , further comprising a driver integrated circuit (IC) for driving at least one of said control vertical FET and said sync vertical FET.

13. The semiconductor package of claim 8 , further comprising a driver IC for driving at least one of said control vertical FET and said sync vertical FET, said conductive carrier being attached to said driver IC.

14. The semiconductor package of claim 1 , wherein said power converter switching stage is implemented as part of a buck converter.

15. A method for fabricating a semiconductor package, said method comprising:
providing a top-drain vertical FET in a first active die, a source of said top-drain vertical FET situated on a source side of said first active die and a drain and a gate of said top-drain vertical FET situated on a drain side of said first active die;
providing a bottom-drain vertical FET in a second active die, a source and a gate of said bottom-drain vertical FET situated on a source side of said second active die and a drain of said bottom-drain vertical FET situated on a drain side of said second active die;
attaching a conductive carrier to said source side of said first active die and to said drain side of said second active die;
utilizing said conductive carrier to couple said source of said top-drain vertical FET to said drain of said bottom-drain vertical FET; and
forming a patterned dielectric over said drain side of said first active die and said source side of said second active die, said patterned dielectric exposing said drain and said gate of said top-drain vertical FET and said source and said gate of said bottom-drain vertical FET.

16. The method claim 15 , wherein said conductive carrier comprises a lead frame.

17. The method claim 15 wherein said top-drain vertical FET and said bottom-drain vertical FET comprise silicon FETs.

18. The method claim 15 , wherein said top-drain vertical FET and said bottom-drain vertical FET comprise III-Nitride FETs.

19. The method claim 15 , further comprising attaching said conductive carrier to a driver integrated circuit (IC) for driving at least one of said top-drain vertical FET and said bottom-drain vertical FET.

20. The method claim 15 , wherein said top-drain vertical FET and said bottom-drain vertical FET are utilized to implement a switching stage of a buck converter.

Assignees

• Int Rectifier Corp
• Infineon Technologies Americas Corp

Inventors

• Cho Eung San
• Sawle Andrew N
• Pavier Mark
• Cutler Daniel

Classifications

• H10W90/736

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W74/111

  the semiconductor body being completely enclosed · CPC title

• H10W72/9413

  on encapsulations · CPC title

• H10W72/944

  Dispositions of multiple bond pads · CPC title

• H10W72/874

  On different surfaces · CPC title