Methods of adding dopants to conductive interconnect structures in substrate technologies and structures formed thereby

Patent metadata

Field	Value
Publication number	US-9394619-B2
Application number	US-201313795042-A
Country	US
Kind code	B2
Filing date	Mar 12, 2013
Priority date	Mar 12, 2013
Publication date	Jul 19, 2016
Grant date	Jul 19, 2016

Abstract

Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods and structures may include forming an opening in a dielectric material of a package substrate, and then plating a conductive interconnect structure in the opening utilizing a plating process. The plating process may comprises a conductive metal and a dopant comprising between about 0.05 and 10 percent weight, wherein the dopant comprises at least one of magnesium, zirconium and zinc.

First claim

What is claimed is:

1. A method of forming a structure comprising:
providing a package substrate;
forming a conductive interconnect structure on a portion of the package substrate, wherein the conductive interconnect structure consists of copper and a dopant, wherein the dopant is selected from a group consisting of magnesium, zirconium, and a combination of magnesium and zirconium, wherein the dopant ranges from about 0.5 percent weight to about 5 percent weight of the conductive interconnect structure, and wherein a grain size of the conductive interconnect structure comprises above about 2 microns.

2. The method of claim 1 further comprising wherein the package substrate comprises a BBUL package substrate.

3. The method of claim 1 further comprising wherein the dopants allow for individual grains of the conductive interconnect structure to rotate within the conductive interconnect structure.

4. The method of claim 1 further comprising wherein a portion of the dopants are located at grain boundaries between individual grains of the conductive interconnect structure.

5. The method of claim 1 further comprising wherein the conductive interconnect structure is formed utilizing a plating process.

6. The method of claim 1 further comprising wherein the conductive interconnect structure comprises a width less than about 10 microns, and wherein the conductive interconnect structure comprises one of a via and a trace.

7. The method of claim 1 further comprising wherein grains of the conductive interconnect structure are capable of viscous glide and rotation.

8. A package structure comprising:
a package substrate;
a conductive interconnect structure disposed on a portion of the package substrate, wherein the conductive interconnect structure consists of copper and a dopant, wherein the dopant is selected from a group consisting of magnesium, zirconium, and a combination of magnesium and zirconium, wherein the dopant has a concentration of less than about 0.18 ppm of the conductive interconnect structure, and wherein a grain size of the conductive interconnect structure comprises above about 2 microns.

9. The package structure of claim 8 further comprising wherein the package substrate comprises a BBUL package substrate.

10. The package structure of claim 8 further comprising wherein the dopants allow for individual grains of the conductive interconnect structure to rotate within the conductive interconnect structure.

11. The package structure of claim 8 further comprising wherein a portion of the dopants are located between individual grains of the conductive interconnect structure.

12. The package structure of claim 8 further comprising wherein the conductive interconnect structure is formed utilizing a plating process.

13. The package structure of claim 8 further comprising wherein the conductive interconnect structure comprises a width less than about 10 microns.

14. The package structure of claim 8 further comprising wherein grains of the conductive interconnect structure are capable of viscous glide and rotation.

15. The package structure of claim 8 further comprising wherein the conductive interconnect structure comprises one of a via and a trace.

16. The package structure of claim 8 further comprising wherein a die is coupled with the package structure.

17. The package structure of claim 8 wherein the package structure further comprises at least one of a CPU and a memory die.

18. The package structure of claim 8 further comprising a system comprising:
a bus communicatively coupled to the package structure; and
an eDRAM communicatively coupled to the bus.

19. A method of forming a structure comprising:
providing a BBUL package substrate;
forming a conductive interconnect structure on a portion of the package substrate, wherein the conductive interconnect structure consists of copper and a dopant, wherein the dopant is selected from a group consisting of magnesium, zirconium, and a combination of magnesium and zirconium, wherein the dopant ranges from about 0.5 percent weight to about 5 percent weight of the conductive interconnect structure, wherein a grain size of the conductive interconnect structure comprises above about 2 microns, and wherein a portion of the dopants are located at grain boundaries between individual grains of the conductive interconnect structure.

20. The method of claim 19 further comprising wherein the dopants allow for individual grains of the conductive interconnect structure to rotate within the conductive interconnect structure.

21. The method of claim 19 further comprising wherein the conductive interconnect structure is formed utilizing a plating process.

22. The method of claim 19 further comprising wherein the conductive interconnect structure comprises a width less than about 10 microns, and wherein the conductive interconnect structure comprises one of a via and a trace.

23. The method of claim 19 further comprising wherein grains of the conductive interconnect structure are capable of viscous glide and rotation.

Assignees

• Intel Corp

Inventors

• Sidhu Rajen S
• Renavikar Mukul P
• Sane Sandeep B

Classifications

• C23C18/48

  Coating with alloys · CPC title

• C25D5/02

  Electroplating of selected surface areas · CPC title

• H05K3/421

  Blind plated via connections (H05K3/422, H05K3/423 and H05K3/425 take precedence) · CPC title

• H05K3/4644

  by building the multilayer layer by layer, i.e. build-up multilayer circuits (making via holes in the insulating layers H05K3/0011; special circuit boards as base or core whereon the multilayer is built H05K3/4602) · CPC title

• C25D3/58 Primary

  containing more than 50% by weight of copper · CPC title