Method of manufacturing a multilayer substrate structure for fine line

Patent metadata

Field	Value
Publication number	US-9370110-B2
Application number	US-201414225682-A
Country	US
Kind code	B2
Filing date	Mar 26, 2014
Priority date	Mar 26, 2014
Publication date	Jun 14, 2016
Grant date	Jun 14, 2016

Abstract

A method of manufacturing a multilayer substrate structure includes the steps of pre-treatment, pressing and post-treatment. A carrier plate provided with a circuit pattern layer is pressed against a plastic sheet. An interlayer connection pad is formed by drilling and filling the lower surface of the plastic sheet. The carrier plate, the plastic sheet, another plastic sheet and another carrier plate with a circuit pattern layer are pressed together, and then drilled/filled to form a multilayer stacked structure such that the two circuit pattern layers are indirectly and electrically connected to the interlayer connection pad, respectively. Therefore, it is possible to overcome the problem due to alignment tolerance by using the interlayer connection pad wider than alignment tolerance, and stacking the circuit layers, each having much finer line and smaller pitch.

First claim

What is claimed is:

1. A method of manufacturing a multilayer substrate structure for fine line, comprising:
a pre-treatment step consisting of a first preparation step, a first pressing step, a first drilling step and a first filling step, wherein the first preparation step consisting of preparing a first plastic sheet and a first carrier plate provided with a first circuit pattern layer, wherein the first circuit pattern layer includes a first circuit pattern and at least one first connection pad; the first pressing step consisting of pressing the first carrier plate against the first plastic sheet to embed the first circuit pattern layer into an upper surface of the first plastic sheet; the first drilling step consisting of forming at least one first opening on a lower surface of the first plastic sheet in alignment with the first connection pad; and the first filling step consisting of filling the first opening with an electrically conductive material to form at least one first connection plug, wherein the first connection plug is connected to the first connection pad, at least one interlayer connection pad is provided on the lower surface of the first plastic sheet and is made from the electrically conductive material, and the interlayer connection pad is connected to the first connection plug so as to form a first stacked structure;
a pressing step consisting of pressing the first stacked structure against a second plastic sheet and a second carrier plate provided with a second circuit pattern layer such that the lower surface of the first plastic sheet is connected to an upper surface of the second plastic sheet, the second circuit pattern layer is embedded into a lower surface of the second plastic sheet, and the interlayer connection pad is embedded into the upper surface of the second plastic sheet, wherein the second circuit pattern layer includes a second circuit pattern and at least one second connection pad, the second connection pad having a shape of a ring with a central region; and
a post-treatment step consisting of a removing step, a second drilling step and a second filling step, the removing step consisting removing the first and second carrier plates such that the first and second circuit pattern layers are exposed to the upper surface of the first plastic sheet and the lower surface of the second plastic sheet, respectively; the second drilling step consisting of drilling the lower surface of the second plastic sheet to form one second opening in alignment with the central region of the second connection pad to stop at the interlayer connection pad; and the second filling step consisting of filling the second opening with the electrically conductive material to form a second connection plug, wherein the second connection plug is connected to the interlayer connection pad so as to form a core stacked structure,
wherein the interlayer connection pad has a width of 40 to 100 μm.

2. The method as claimed in claim 1 , further comprising:
a third pressing step to press a third plastic sheet and a fourth plastic sheet on the top and the bottom of the core stacked structure;
a third preparation step is to form third connection plugs in the third plastic sheet and fourth connection plugs in the fourth plastic sheet by using drilling and filling, then to form second interlayer connection pads corresponding to the third connection plugs on the upper surface of the third plastic sheet, and to form third interlayer connection pads corresponding to the fourth connection plugs on the lower surface of the fourth plastic sheet, such that a pre-laminating structure is formed, wherein the third connection plugs and the fourth connection plugs are connecting to the first connection pads and the second connection pads, respectively, and to form a second stacked structure and a third stacked structure as the first preparation step, wherein the second stacked structure includes a third carrier plate, a third circuit pattern layer formed on the lower surface of the third carrier plate, and a fifth plastic sheet; the third circuit pattern layer includes a third circuit pattern and a third connection pad in form of a ring, and is embedded into the upper surface of the fifth plastic sheet, and the third stacked structure includes a fourth carrier plate, a fourth circuit pattern layer formed on the upper surface of the fourth carrier plate, and a sixth plastic sheet, the fourth circuit pattern layer includes a fourth circuit pattern and a fourth connection pad in form of a ring, and is embedded into the lower surface of the sixth plastic sheet;
a fourth pressing step is to press the second stacked structure and the third stacked structure against the upper and lower surfaces of pre-laminating structure, respectively;
a third removing step is to remove the third carrier plate, the fourth carrier plate such that the third circuit pattern layer and the fourth circuit pattern layer are exposed to the upper surface of the fifth plastic sheet and the lower surface of the sixth plastic sheet, respectively, and
a post-laminating process step is to form fifth and sixth openings at the center of the third connection pads and the fourth connection pads, respectively, then to form fifth connection plugs and sixth connection plugs which are connected to the second interlayer connection pads and the third interlayer connection pads, respectively, by plating the conductive material,
wherein the width of the second interlayer connection pads and the third interlayer connection pads is 40˜100 μm.

3. The method as claimed in claim 2 , wherein an electroplated seed layer is formed between the third carrier plate and the third circuit pattern layer, and between the fourth carrier plate and the fourth circuit pattern layer, and the electroplated seed layers are removed in the third removing step.

4. The method as claimed in claim 2 , wherein post-laminating process step further comprising a step of forming solder mask, wherein a first solder mask and a second solder mask are formed on the upper surface of the fifth plastic sheet and the lower surface of the sixth plastic sheet, respectively, the first solder mask covers the third circuit pattern layer and part of the third connection pad, and the second solder mask covers the fourth circuit pattern layer and part of the fourth connection pad.

5. The method as claimed in claim 2 , wherein each of the first, second, third and fourth carrier plates is selected from a group consisting of stainless steel and aluminum with surface roughness defined by Ra<0.35 μm and Rz<3 μm.

6. The method as claimed in claim 1 , further comprising a step of forming solder mask, wherein a first solder mask and a second solder mask are formed on the upper surface of the first plastic sheet and the lower surface of the second plastic sheet, respectively, the first solder mask covers the first circuit pattern layer and part of the at least one first connection pad, and the second solder mask covers the second circuit pattern layer and part of the at least one second connection pad.

7. The method as claimed in claim 1 , wherein an electroplated seed layer is formed between the first circuit pattern layer and the first carrier plate, and another electroplated seed layer between the second circuit pattern layer and the second carrier plate, and the electroplated seed layers are removed in the step of removing.

Assignees

• Kinsus Interconnect Tech Corp

Inventors

• Lin Ting-Hao
• Lu Yu-Te

Classifications

• H05K3/0094

  Filling or covering plated through-holes or blind plated vias, e.g. for masking or for mechanical reinforcement · CPC title

• H05K3/3452 Primary

  Solder masks · CPC title

• H05K3/4611 Primary

  by laminating two or more circuit boards (H05K3/4652 takes precedence) · CPC title

• H05K2203/06

  Lamination · CPC title

• H05K2203/0723

  Electroplating, e.g. finish plating · CPC title