Printed circuit board and method for manufacturing same

US9363883B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9363883-B2
Application numberUS-201113997420-A
CountryUS
Kind codeB2
Filing dateDec 23, 2011
Priority dateDec 24, 2010
Publication dateJun 7, 2016
Grant dateJun 7, 2016

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A printed circuit board according to an embodiment of the present invention includes an insulating layer, a pad formed on the insulating layer and exposed through an opening section of a solder resist, a bump formed by filling an opening portion of the solder resist from top of the pad and having an narrow width than the opening of the solder resist.

First claim

Opening claim text (preview).

What is claimed is: 1. A printed circuit board comprising; an insulating layer; a pad formed on the insulating layer; a solder resist formed on the pad and having an opening section exposing an upper surface of the pad; a bump connection section on the pad and filling the opening section of the solder resist; a plating seed layer between an inner wall of the solder resist and a side surface of the bump connection section; and a bump formed on the bump connection section, having a first portion protruded from an upper surface of the solder resist at a predetermined height, wherein the first portion of the bump has a narrower width than the opening section of the solder resist. 2. The printed circuit board of claim 1 , wherein an upper surface of the bump connection section has a narrower width than a lower surface of the bump connection section. 3. The printed circuit board of claim 1 , wherein the bump connection section protrudes from the upper surface of the solder resist. 4. The printed circuit board of claim 3 , wherein the bump is formed narrower than the width of a lower surface of the bump connection section. 5. The printed circuit board of claim 3 , wherein a lower surface of the bump is higher than an upper surface of the plating seed layer. 6. The printed circuit board of claim 3 , wherein the bump connection section is formed such that a width of an upper surface thereof and a lower surface opposite the upper surface is different. 7. The printed circuit board of claim 3 , wherein the bump is not in direct contact with the plating layer. 8. The printed circuit board of claim 7 , wherein the solder is formed such that a width of an upper surface thereof and a lower surface opposite the upper surface is same. 9. The printed circuit board of claim 7 , wherein a width of a lower surface of the solder is same as a width of an upper surface of the bump. 10. The printed circuit board of claim 1 , wherein the plating seed layer protrudes from the upper surface of the solder resist. 11. The printed circuit board of claim 1 , wherein the bump is formed such that a width of the upper surface thereof and a lower surface opposite the upper surface is equal. 12. The printed circuit board of claim 1 , wherein the bump is a cylinder pillar, a square pillar and a polygonal pillar in shape. 13. The printed circuit board of claim 1 , wherein the bump is made of alloy containing copper.

Assignees

Inventors

Classifications

  • Solder masks · CPC title

  • Metallic bump or raised conductor not used as solder bump · CPC title

  • having an array of bottom contacts, e.g. pad grid array or ball grid array components · CPC title

  • Forming printed elements for providing electric connections to or between printed circuits · CPC title

  • H05K3/4007Primary

    Surface contacts, e.g. bumps (H05K3/4092 takes precedence; deposition of finish layers on pads H05K3/24; forming solder bumps H05K3/3465) · CPC title

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Frequently asked questions

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What does patent US9363883B2 cover?
A printed circuit board according to an embodiment of the present invention includes an insulating layer, a pad formed on the insulating layer and exposed through an opening section of a solder resist, a bump formed by filling an opening portion of the solder resist from top of the pad and having an narrow width than the opening of the solder resist.
Who is the assignee on this patent?
Ryu Sung Wuk, Shim Seong Bo, Shin Seung Yul, and 1 more
What technology area does this patent fall under?
Primary CPC classification H05K3/4007. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Jun 07 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).