SiC semiconductor device
US-12080760-B2 · Sep 3, 2024 · US
Junction FET semiconductor device with dummy mask structures for improved dimension control and method for forming the same
US9196751B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9196751-B2 |
| Application number | US-201313861523-A |
| Country | US |
| Kind code | B2 |
| Filing date | Apr 12, 2013 |
| Priority date | Mar 14, 2013 |
| Publication date | Nov 24, 2015 |
| Grant date | Nov 24, 2015 |
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Abstract
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A method for simultaneously forming JFET devices and MOSFET devices on a substrate includes using gate structures which serve as active gate structures in the MOSFET region, as dummy gate structures in the JFET portion of the device. The dummy gate electrodes are used as masks and determine the spacing between gate regions and source/drain regions, the width of the gate regions, and the spacing between adjacent gate regions according to some embodiments. The transistor channel is therefore accurately dimensioned.
First claim
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What is claimed is: 1. A semiconductor device comprising: a substrate; a JFET transistor comprising a gate region of one polarity disposed in said substrate and source and drain regions of opposite polarity also disposed in said substrate and spaced apart from said gate region, wherein said source region is spaced apart from said gate region in said substrate by a source-gate link region having a first length and said drain region is spaced apart from said gate region in said su…
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Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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- What does patent US9196751B2 cover?
- A method for simultaneously forming JFET devices and MOSFET devices on a substrate includes using gate structures which serve as active gate structures in the MOSFET region, as dummy gate structures in the JFET portion of the device. The dummy gate electrodes are used as masks and determine the spacing between gate regions and source/drain regions, the width of the gate regions, and the spacing…
- Who is the assignee on this patent?
- Taiwan Semiconductor Mfg Co Ltd
- What technology area does this patent fall under?
- Primary CPC classification H10D30/83. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Nov 24 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).