Integrated circuit package stacking system with shielding and method of manufacture thereof

Patent metadata

Field	Value
Publication number	US-9355939-B2
Application number	US-71626910-A
Country	US
Kind code	B2
Filing date	Mar 2, 2010
Priority date	Mar 2, 2010
Publication date	May 31, 2016
Grant date	May 31, 2016

Abstract

A method of manufacture of an integrated circuit package system includes: providing a base package substrate including: forming component contacts on a component side of the base package substrate, forming system contacts on a system side of the base package substrate, and forming a reference voltage circuit between the component contacts and the system contacts; mounting a first integrated circuit die on the component contacts; mounting a lead frame on the first integrated circuit die and coupled to the component contacts; and isolating a conductive shield from the lead frame, the conductive shield coupled to the reference voltage circuit.

First claim

What is claimed is:

1. A method of manufacture of an integrated circuit package system comprising:
providing a base package substrate including:
forming component contacts on a component side of the base package substrate,
forming system contacts on a system side of the base package substrate, and
forming a reference voltage circuit between the component contacts and the system contacts;

mounting a first integrated circuit die on the component contacts;
mounting a lead frame on the first integrated circuit die and coupled to the component contacts;
isolating a conductive shield, with integrated vertical coupling leads, from the lead frame, the conductive shield mounted in direct contact with the first integrated circuit die and the integrated vertical coupling leads coupled to the reference voltage circuit;
forming a base package body, with vertical sides coplanar with vertical edges of the base package substrate, including embedding the integrated vertical coupling leads by completely filling the conductive shield that is exposed from and surrounded by a planar peripheral region of the base package body; and
exposing an array of pillar interconnects coplanar with the planar peripheral region of the base package body, each including a surface exposed from the planar peripheral region and the surfaces showing signs of having been sawed, ground, or etched.

2. The method as claimed in claim 1 further comprising providing an array of coupling leads on the lead frame.

3. The method as claimed in claim 1 wherein forming the base package body includes forming the base package body on the pillar interconnects and between the lead frame and the base package substrate.

4. The method as claimed in claim 1 further comprising forming pillar interconnects from the lead frame.

5. The method as claimed in claim 1 further comprising mounting a stacked integrated circuit package over the first integrated circuit die including providing the conductive shield between the stacked integrated circuit package and the first integrated circuit die.

6. A method of manufacture of an integrated circuit package system comprising:
providing a base package substrate including:
forming component contacts on a component side of the base package substrate,
forming system contacts on a system side of the base package substrate, and
forming a reference voltage circuit between the component contacts and the system contacts by coupling two adjacent units of the component contacts to the closest unit of the system contacts;

mounting a first integrated circuit die on the component contacts including coupling a chip interconnect to one of the component contacts of the reference voltage circuit;
mounting a lead frame on the first integrated circuit die and coupled to the component contacts including applying a conductive adhesive between the lead frame and one of the component contacts of the reference voltage circuit;
isolating a conductive shield, with integrated vertical coupling leads, from the lead frame by sawing, grinding or etching including having the conductive shield mounted in direct contact with the first integrated circuit die and the integrated vertical coupling leads coupled to the reference voltage circuit;
forming a base package body, with vertical sides coplanar with vertical edges of the base package substrate, including embedding the integrated vertical coupling leads by completely filling the conductive shield that is exposed from and surrounded by a planar peripheral region of the base package body; and
exposing an array of pillar interconnects coplanar with the planar peripheral region of the base package body, each including a surface exposed from the planar peripheral region and the surfaces showing signs of having been sawed, ground, or etched.

7. The method as claimed in claim 6 wherein isolating the conductive shield from the lead frame by sawing, grinding or etching includes applying a rotating saw, a grinding wheel, or a chemical etch to the lead frame.

8. The method as claimed in claim 6 wherein forming the base package body includes forming the base package body on the pillar interconnects and between the lead frame and the base package substrate by injecting a molding compound.

9. The method as claimed in claim 6 further comprising forming a finished surface including sawing, grinding, or etching a base package body to be coplanar with the pillar interconnects.

10. The method as claimed in claim 6 further comprising mounting a stacked integrated circuit package over the first integrated circuit die including providing the conductive shield between the stacked integrated circuit package and the first integrated circuit die includes coupling a system interconnect to the reference voltage circuit.

11. An integrated circuit package system comprising:
a base package substrate including:
component contacts on a component side of the base package substrate,
system contacts on a system side of the base package substrate, and
a reference voltage circuit connected between the component contacts and the system contacts;

a first integrated circuit die mounted on the component contacts;
a conductive shield, with integrated vertical coupling leads, mounted in direct contact with the first integrated circuit die and the integrated vertical coupling leads coupled to the reference voltage circuit through the component contacts;
a base package body, with vertical sides coplanar with vertical edges of the base package substrate, formed to embed the integrated vertical coupling leads and completely fill the conductive shield that is exposed from and surrounded by a planar peripheral region of the base package body; and
an array of pillar interconnects coplanar with and exposed from the planar peripheral region of the base package body, each including a surface exposed from the planar peripheral region and the surfaces showing signs of having been sawed, ground, or etched.

12. The system as claimed in claim 11 wherein the array of pillar interconnects surrounds the conductive shield.

13. The system as claimed in claim 11 wherein the base package body is formed on the pillar interconnects and between the conductive shield and the base package substrate.

14. The system as claimed in claim 11 further comprising internal circuitry between the component contacts and the system contacts in the base package substrate.

15. The system as claimed in claim 11 further comprising a stacked integrated circuit package over the first integrated circuit die.

16. The system as claimed in claim 11 further comprising:
a chip interconnect between the first integrated circuit die and the reference voltage circuit; and
a conductive adhesive between the conductive shield and the reference voltage circuit.

17. The system as claimed in claim 16 wherein the array of pillar interconnects surrounds the conductive shield wherein the conductive adhesive is between the pillar interconnects and the component contacts.

18. The system as claimed in claim 16 wherein the base package body is formed on the pillar interconnects and between the conductive shield and the base package substrate in which the first integrated circuit die, the chip interconnects, and the component side are encapsulated.

19. The system as claimed in claim 16 further comprising internal circuitry between the component contacts and the system contacts in the base package substrate, the internal circuitry includes internal traces, vias, or a combination thereof.

Assignees

• Cho Namju
• Chi Heejo
• Shin Hangil
• Stats Chippac Ltd

Inventors

• Cho Namju
• Chi Heejo
• Shin Hangil

Classifications

• H10W90/756

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/736

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/732

  between stacked chips · CPC title