Assembly structure for connecting multiple dies into a system-in-package chip and the method thereof

Patent metadata

Field	Value
Publication number	US-9349610-B2
Application number	US-201514794820-A
Country	US
Kind code	B2
Filing date	Jul 9, 2015
Priority date	Apr 16, 2014
Publication date	May 24, 2016
Grant date	May 24, 2016

Abstract

A method for assembling multiple integrated circuit dies into a system-in-package chip is disclosed, the method comprising: providing a plurality of integrated circuit dies; disposing at least one redistribution layer on at least one of the plurality of integrated circuit dies for making wire connections among the plurality of integrated circuit dies without using a substrate underneath the plurality of integrated circuit dies; establishing wire connections among the plurality of integrated circuit dies and verifying the plurality of wire connections; and packaging the plurality of integrated circuit dies and the verified wire connections into a system-in-package chip.

First claim

The invention claimed is:

1. A method for assembling multiple integrated circuit dies into a system-in-package chip, the method comprising:
(a) providing a plurality of integrated circuit dies;
(b) disposing at least one redistribution layer on at least one of the plurality of integrated circuit dies for making wire connections among the plurality of integrated circuit dies without using a substrate underneath the plurality of integrated circuit dies;
(c) establishing wire connections among the plurality of integrated circuit dies and verifying the plurality of wire connections; and
(d) packaging the plurality of integrated circuit dies and the verified wire connections into a system-in-package chip.

2. The system-in-package chip according to claim 1 , wherein the plurality of integrated circuit dies comprises a first integrated circuit die and a second integrated circuit die, wherein the first integrated circuit die and the second integrated circuit die are in two different power domains.

3. The circuit according to claim 2 , wherein the first integrated circuit die comprises mainly digital circuits and the second integrated circuit die comprises mainly analog circuits.

4. The circuit according to claim 2 , a first pad on the first redistribution layer is electrically connected to a first terminal of the second integrated circuit die by wire bonding.

5. The method according to claim 1 , wherein the plurality of integrated circuit dies comprises a first integrated circuit die and a second integrated circuit die, wherein the second integrated circuit die is disposed on the first integrated circuit die through an isolation layer.

6. The circuit according to claim 5 , a first pad on the first redistribution layer is electrically connected to a first terminal of the second integrated circuit die by wire bonding.

7. The circuit according to claim 6 , wherein the first pad is used for electrically connecting the first terminal of the second integrated circuit die to an external lead.

8. The method according to claim 1 , wherein a first redistribution layer is disposed on a first integrated die with at least one pad thereon for connecting to a second integrated circuit die, wherein step (a) further comprising disposing a diode underneath each of the at least one pad in the first integrated circuit die, wherein a negative terminal of the diode is electrically connected to a corresponding pad of the at least one pad on the first redistribution layer for connecting to the second integrated circuit die and a positive terminal of the diode is electrically connected to the first substrate of the first integrated circuit die for connecting to a ground node.

9. The method according to claim 8 , wherein the first substrate is p-type, and the diode is disposed by creating an n-type region in the p-type substrate to form a p-n junction between the p-type substrate and the n-type region, wherein the n-type region is electrically connected to a corresponding pad of the at least one pad.

10. The method according to claim 8 , wherein each of the at least one pad is a floating pad before the at least one diode is disposed in the first substrate, and the system-in-package chip has a plurality of pins, wherein each of the at least one pad is electrically connected to a corresponding pin of the plurality of pins.

Assignees

• Whang Tsung Chuan
• Wang Yi-Chieh
• Global Unichip Corp
• Taiwan Semiconductor Mfg

Inventors

• Whang Tsung Chuan
• Wang Yi-Chieh

Classifications

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/752

  between stacked chips · CPC title

• H10W90/732

  between stacked chips · CPC title

• H10W90/28

  the stacked chips having different sizes, e.g. chip stacks having a pyramidal shape · CPC title

• H10W72/9415

  relative to the surface, e.g. recessed, protruding · CPC title