Stacked semiconductor device, and method and apparatus of manufacturing the same

US9343292B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9343292-B2
Application numberUS-201414220557-A
CountryUS
Kind codeB2
Filing dateMar 20, 2014
Priority dateMar 21, 2013
Publication dateMay 17, 2016
Grant dateMay 17, 2016

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

Provided is a method of manufacturing a stacked semiconductor device, which includes forming a stacked film on a semiconductor substrate, the stacked film including a plurality of silicon oxide films and a plurality of silicon nitride films, which are alternately arranged on top of each other, and the stacked film being obtained by repeatedly performing a series of operations of forming the silicon oxide film on the semiconductor substrate using one of triethoxysilane, octamethylcyclotetrasiloxane, hexamethyldisilazane and diethylsilane gases, and forming the silicon nitride film on the formed silicon oxide film; etching the silicon nitride films in the stacked film; removing carbons contained in the silicon oxide films, which are not removed in the etching, to reduce a concentration of the carbons; and forming electrodes in regions where the silicon nitride films are etched in the etching.

First claim

Opening claim text (preview).

What is claimed is: 1. A method of manufacturing a stacked semiconductor device, comprising: forming a stacked film on a semiconductor substrate, the stacked film including a plurality of silicon oxide films and a plurality of silicon nitride films, which are alternately arranged on top of each other, and the stacked film being obtained by repeatedly performing a series of operations of forming the silicon oxide film on the semiconductor substrate using one of triethoxysilane, octamethylcyclotetrasiloxane, hexamethyldisilazane and diethylsilane gases, and forming the silicon nitride film on the formed silicon oxide film; etching the silicon nitride films in the stacked film; after etching the silicon nitride films, removing carbons contained in the silicon oxide films, which are not removed in the etching, to reduce a concentration of the carbons; and forming electrodes in regions where the silicon nitride films are etched in the etching. 2. The method of claim 1 , wherein removing includes supplying hydrogen and oxygen gases into the silicon oxide films. 3. The method of claim 1 , wherein removing is performed after a shaping process of the stacked semiconductor device. 4. A stacked semiconductor device manufactured by the method of claim 1 .

Assignees

Inventors

Classifications

  • H10P95/00Primary

    Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass · CPC title

  • the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz · CPC title

  • the material being a silicon oxide, e.g. SiO2 · CPC title

  • the compound being a molecule comprising at least one silicon-oxygen bond and the compound having hydrogen or an organic group attached to the silicon or oxygen, e.g. a siloxane · CPC title

  • the compound being a silane, e.g. disilane, methylsilane or chlorosilane · CPC title

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What does patent US9343292B2 cover?
Provided is a method of manufacturing a stacked semiconductor device, which includes forming a stacked film on a semiconductor substrate, the stacked film including a plurality of silicon oxide films and a plurality of silicon nitride films, which are alternately arranged on top of each other, and the stacked film being obtained by repeatedly performing a series of operations of forming the sil…
Who is the assignee on this patent?
Tokyo Electron Ltd
What technology area does this patent fall under?
Primary CPC classification H10P95/00. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue May 17 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).