Nonvolatile semiconductor memory device

Patent metadata

Field	Value
Publication number	US-9343115-B2
Application number	US-201514656689-A
Country	US
Kind code	B2
Filing date	Mar 12, 2015
Priority date	Oct 30, 2012
Publication date	May 17, 2016
Grant date	May 17, 2016

Abstract

A memory array includes a resistive memory cell array having a first cell transistor and a resistance change element connected in series and a reference cell array having a second cell transistor and a resistance element connected in series. The second cell transistor of the reference cell array is connected to a reference source line, and the resistance element is connected to a reference bit line. A dummy memory cell is connected to the reference bit line in the memory cell array, and both ends of a resistance change element of the dummy memory cell are short-circuited through the reference bit line.

First claim

What is claimed is:

1. A nonvolatile semiconductor memory device, comprising:
a word line;
a first data line;
a second data line;
a plurality of memory cells each having a first cell transistor and a first resistance change element connected in series between the first data line and the second data line, a gate of the first cell transistor being connected to the word line;
a reference word line;
a first reference data line;
a second reference data line;
a reference cell having a second cell transistor and a resistance element connected in series between the first reference data line and the second reference data line, a gate of the second cell transistor being connected to the reference word line; and
a dummy memory cell having a third cell transistor and a second resistance change element,

wherein
in the dummy memory cell, both ends of the second resistance change element are connected to the first reference data line, and one end of the third cell transistor is connected to one end of the second resistance change element.

2. The nonvolatile semiconductor memory device of claim 1 , wherein one end of the third cell transistor that is not connected to the first reference data line is open, and a gate of the third cell transistor is connected to the word line.

3. The nonvolatile semiconductor memory device of claim 1 , wherein the first cell transistor, the second cell transistor, and the third cell transistor have the same gate oxide film thickness.

4. The nonvolatile semiconductor memory device of claim 1 , wherein the first cell transistor, the second cell transistor, and the third cell transistor have the same gate channel length and gate channel width.

5. The nonvolatile semiconductor memory device of claim 1 , further comprising:
a sense amplifier that determines data stored in the plurality of memory cells; and
a column gate that selects the first data line and the first reference data line and connects the selected lines to the sense amplifier.

6. The nonvolatile semiconductor memory device of claim 1 , further comprising:
a sense amplifier that determines data stored in the plurality of memory cells; and
a column gate that selects the second data line and the second reference data line and connects the selected lines to the sense amplifier.

7. The nonvolatile semiconductor memory device of claim 1 , wherein at least one of the first data line and the second data line is placed to run orthogonally to the reference word line, and
at least one of the first reference data line and the second reference data line is placed to run orthogonally to the word line.

8. The nonvolatile semiconductor memory device of claim 1 , wherein, in the dummy memory cell, the first reference data line includes first and second interconnects placed to run in parallel with each other in upper and lower wiring layers, respectively, with respect to the second resistance change element,
the second resistance change element is connected to the first interconnect at one end and to the second interconnect at the other end, and
the first and second interconnects are short-circuited every plural word lines.

9. The nonvolatile semiconductor memory device of claim 1 , wherein each of the plurality of memory cells is a resistive memory cell where the first resistance change element is formed of a resistance change element.

10. The nonvolatile semiconductor memory device of claim 1 , wherein each of the plurality of memory cells is a magnetoresistive memory cell where the first resistance change element is formed of a magnetoresistance change element.

11. The nonvolatile semiconductor memory device of claim 1 , wherein each of the plurality of memory cells is a phase change memory cell where the first resistance change element is formed of a phase change element.

12. The nonvolatile semiconductor memory device of claim 1 , wherein the dummy memory cell includes a wiring layer and a contact connected with the wiring layer, and
a plurality of the dummy memory cells are arranged at substantially the same intervals as intervals at which the plurality of memory cells are arranged.

Assignees

• Panasonic Ip Man Co Ltd

Inventors

• Ueda Takanori
• Kouno Kazuyuki
• Murakuki Yasuo
• Nakayama Masayoshi
• Ishitobi Yuriko
• Takahashi Keita

Classifications

• G11C11/5607

  using magnetic storage elements · CPC title

• G11C7/14

  Dummy cell management; Sense reference voltage generators · CPC title

• G11C11/15

  using multiple magnetic layers (G11C11/155 takes precedence) · CPC title

• G11C5/08 Primary

  for interconnecting magnetic elements, e.g. toroidal cores · CPC title

• G11C11/14

  using thin-film elements · CPC title