Resistance-change semiconductor memory

Patent metadata

Field	Value
Publication number	US-9583537-B2
Application number	US-201514970230-A
Country	US
Kind code	B2
Filing date	Dec 15, 2015
Priority date	Jul 5, 2010
Publication date	Feb 28, 2017
Grant date	Feb 28, 2017

Abstract

According to one embodiment, a memory includes first to fourth memory cells aligned in a first direction. Each of the first to fourth memory cells comprises a cell transistor having a gate connected to a word line extending in a second direction crossing the first direction and a resistive memory element having one end connected to a first source/drain region of the cell transistor. A second source/drain region of the cell transistor is connected to one of a first bit line extending in the first direction and a second bit line extending in the second direction. The other end of the resistive memory element is connected to one of the first and second bit lines which is apart from the second source/drain region. The second source/drain regions in the first and second memory cells are shared, and the second source/drain regions in the third and fourth memory cells are shared.

First claim

What is claimed is:

1. A resistance-change semiconductor memory comprising first to fourth memory cells aligned in a first direction,
wherein each of the first to fourth memory cells comprises a cell transistor having a gate connected to a word line extending in a second direction crossing the first direction,
a second source/drain region of the cell transistor is connected to one of a first bit line extending in the first direction and a second bit line extending in the second direction,
an end of the a resistive memory element is connected to one of the first and second bit lines which is not connected to the second source/drain region,
the second source/drain regions in the first and second memory cells are shared, and the second source/drain regions in the third and fourth memory cells are shared, and
the first and second memory cells are arranged in a first element region, and the third and fourth memory cells are arranged in a second element region different from the first element region.

2. The memory of claim 1 , wherein each of the first to fourth memory cells comprises the resistive memory element, and
when the second source/drain region of the cell transistor is connected to the first bit line and the end of the resistive memory element is connected to the second bit line, the second bit line connected to the resistive memory element in the second memory cell and the second bit line connected to the resistive memory element in the third memory cell are shared.

3. The memory of claim 1 , wherein each of the first to fourth memory cells comprises the resistive memory element, and the resistive memory element is a magnetoresistive element.

4. The memory of claim 1 , further comprising: a memory cell array comprising columns aligned in the second direction and extending in the first direction; and a control circuit which controls reading/writing with respect to the memory cell array, wherein each of the columns includes the first to fourth memory cells; and wherein the control circuit executes the reading/writing with respect to the memory cells in one row of the memory cell array at the same time.

5. The memory of claim 1 , further comprising: a memory cell array comprising columns aligned in the second direction and extending in the first direction; and a control circuit which controls reading/writing with respect to the memory cell array, wherein each of the columns includes the first to fourth memory cells; and wherein the control circuit sets all of the memory cells in one row of the memory cell array to a first state and then changes predetermined memory cells in the memory cells to a second state from the first state.

6. A resistance-change semiconductor memory comprising first to fourth memory cells aligned in a first direction,
wherein each of the first to fourth memory cells comprises a cell transistor having a gate connected to a word line extending in a second direction crossing the first direction,
a second source/drain region of the cell transistor is connected to one of a first bit line extending in the first direction and a second bit line extending in the second direction,
an end of a resistive memory element is connected to one of the first and second bit lines which is not connected to the second source/drain region,
the second source/drain regions in the first and second memory cells are shared, and the second source/drain regions in the third and fourth memory cells are shared,
the first to fourth memory cells are arranged in an element region common to them, and
a cell isolation transistor is connected to a portion between the first source/drain region in the second memory cell and the first source/drain region in the third memory cell.

7. The memory of claim 6 , wherein each of the first to fourth memory cells comprises the resistive memory element, and
when the second source/drain region of the cell transistor is connected to the first bit line and the end of the resistive memory element is connected to the second bit line, the second bit line connected to the resistive memory element in the second memory cell and the second bit line connected to the resistive memory element in the third memory cell are shared.

8. The memory of claim 6 , wherein the cell isolation transistor is off during at least reading/writing.

9. The memory of claim 8 , wherein a gate potential which turns off the cell isolation transistor is less than or equal to a gate potential of the cell transistor in each non-selected cell.

10. The memory of claim 6 , wherein each of the first to fourth memory cells comprises the resistive memory element, and the resistive memory element is a magnetoresistive element.

11. The memory of claim 6 , further comprising: a memory cell array comprising columns aligned in the second direction and extending in the first direction; and a control circuit which controls reading/writing with respect to the memory cell array, wherein each of the columns includes the first to fourth memory cells; and wherein the control circuit executes the reading/writing with respect to the memory cells in one row of the memory cell array at the same time.

12. The memory of claim 6 , further comprising: a memory cell array comprising columns aligned in the second direction and extending in the first direction; and a control circuit which controls reading/writing with respect to the memory cell array, wherein each of the columns includes the first to fourth memory cells; and wherein the control circuit sets all of the memory cells in one row of the memory cell array to a first state and then changes predetermined memory cells in the memory cells to a second state from the first state.

13. A resistance-change semiconductor memory comprising first to fourth memory cells aligned in a first direction,
wherein each of the first to fourth memory cells comprises: a first cell transistor having a gate connected to a first word line extending in a second direction crossing the first direction, and a second cell transistor having a gate connected to a second word line extending in the second direction,
a second source/drain region of the first cell transistor and a third source/drain of the second cell transistor are connected to one of a first bit line extending in the first direction and a second bit line extending in the second direction,
an end of a resistive memory element is connected to one of the first and second bit lines which is not connected to the second source/drain region;
the second source/drain regions in the first and second memory cells are shared, the third source/drain regions in the second and the third memory cells are shared and the second source/drain regions in the third and fourth memory cells are shared, and
the first to fourth memory cells are arranged in an element region common to them.

14. The memory of claim 13 , wherein each of the first to fourth memory cells comprises the resistive memory element, and the resistive memory element is a magnetoresistive element.

15. The memory of claim 13 , further comprising: a memory cell array comprising columns aligned in the second direction and extending in the first direction; and a control circuit which controls reading/writing with respect to the memory cell array, wherein each of the columns includes the first to fourth memory cells; and wherein the control circuit executes the reading/writing with respect to the memory cells in one row of the memory cell array at the same time.

16. The memory of claim 13 , further comprising: a memory cell array comprising columns aligned in the second direction and extending

Assignees

• Toshiba Kk

Inventors

• Inaba Tsuneo

Classifications

• G11C11/1693

  Timing circuits or methods · CPC title

• G11C5/08

  for interconnecting magnetic elements, e.g. toroidal cores · CPC title

• G11C5/06

  Arrangements for interconnecting storage elements electrically, e.g. by wiring · CPC title

• G11C11/00

  Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor (G11C14/00 - G11C21/00 take precedence) · CPC title

• G11C11/02

  using magnetic elements · CPC title