Semiconductor system for implementing an ising model of interaction

Patent metadata

Field	Value
Publication number	US-9588911-B2
Application number	US-201514642266-A
Country	US
Kind code	B2
Filing date	Mar 9, 2015
Priority date	Aug 29, 2014
Publication date	Mar 7, 2017
Grant date	Mar 7, 2017

Abstract

In a semiconductor device which calculates an interaction model, a technique capable of executing interaction calculation in non-synchronization with a clock is provided. The semiconductor device includes a plurality of units each of which includes: a first memory cell for storing a value indicating a state of one node of an interaction model; a second memory cell for storing an interaction coefficient indicating an interaction from a node connected to the one node; and an interaction calculation circuit for determining a value indicating a next state of the one node based on a current determined by a value indicating a state of the connected node and the interaction coefficient.

First claim

What is claimed is:

1. A semiconductor device comprising:
a plurality of units each of which includes a first memory cell for storing a value indicating a state of one node of an interaction model, a second memory cell for storing an interaction coefficient indicating an interaction from a node connected to the one node, and an interaction calculation circuit for determining a value indicating a next state of the one node based on a current determined by a value indicating a state of the connected node and the interaction coefficient;
wherein the interaction calculation circuit is controlled by an interaction signal which enables or disables execution of interaction; and
wherein the interaction calculation circuit includes:
a logic circuit which adds currents of a first value and a second value based on the value indicating the state of the connected node and the interaction coefficient; and
a comparison circuit which compares the added currents based on a result of the logic circuit, and outputs the first value or the second value as the value indicating the next state of the one node.

2. The semiconductor device according to claim 1 ,
wherein the logic circuit includes: a first calculation circuit which adds the current of the first value and which is configured of a plurality of parallel-connected current paths configured of a plurality of MOS transistors each of which is gate-controlled based on the value indicating the state of the connected node and the interaction coefficient; and a second calculation circuit which adds the current of the second value and which is configured of a plurality of parallel-connected current paths configured of a plurality of MOS transistors each of which is gate-controlled based on the value indicating the state of the connected node and the interaction coefficient,
the comparison circuit is configured of combination of a current mirror circuit configured of a MOS transistor, which compares a current of a first current comparison line on which a result of the first calculation circuit appears and a current of a second current comparison line on which a result of the second calculation circuit appears, and which outputs the first value or the second value corresponding to a larger current as the value indicating the next state of the one node.

3. The semiconductor device according to claim 2 ,
wherein, in the interaction calculation circuit,
the currents in the first calculation circuit and the second calculation circuit are added in a period when the interaction signal enables the execution of the interaction so as to change the value indicating the next state of the one node in the comparison circuit, and
currents in the first calculation circuit and the second calculation circuit are turned OFF in a period when the interaction signal disables the execution of the interaction.

4. The semiconductor device according to claim 1 ,
wherein the interaction calculation circuit includes a writing circuit which writes the first value or the second value, which is outputted from the comparison circuit, into the first memory cell, and the writing circuit is controlled by the interaction signal.

5. The semiconductor device according to claim 1 ,
wherein each of the plurality of units includes a generation circuit for generating the interaction signal, and a unit for updating the value indicating the state of the node is limited based on the interaction signal generated in the generation circuit.

6. The semiconductor device according to claim 5 ,
wherein, in each of the plurality of units, simultaneous updating of an adjacent unit is prohibited based on the interaction signal.

7. The semiconductor device according to claim 6 ,
wherein the generation circuit includes a logic circuit which generates the interaction signal by using an address signal.

8. An information processing device to which a semiconductor device capable of operating as a CPU, a RAM, a HDD, and an accelerator is connected via a system bus,
wherein the semiconductor device includes:
a plurality of units each of which includes a first memory cell for storing a value indicating a state of one node of an interaction model, a second memory cell for storing an interaction coefficient indicating an interaction from a node connected to the one node, and an interaction calculation circuit for determining a value indicating a next state of the one node based on a current determined by a value indicating a state of the connected node and the interaction coefficient;
an I/O interface which performs reading from/writing to a memory cell of the plurality of units; and
an interaction control interface which supplies a signal for enabling interaction to the plurality of units, and,
in a control program of the semiconductor device executed on the CPU,
the value indicating the state of the node and the interaction coefficient are written into the plurality of units on the semiconductor device to which each node of the interaction model expressing a target problem is assigned,
a processing of ground state search for the plurality of units is repeatedly executed during predetermined time, and
the value indicating the state of the node of the plurality of units which has reached the ground state is read, so that a solution for the target problem is obtained.

9. The information processing device according to claim 8 ,
wherein the processing of the ground state search for the plurality of units is controlled by an interaction signal which enables or disables execution of interaction.

10. The information processing device according to claim 9 ,
wherein the processing of the ground state search for the plurality of units
changes the value indicating the state of the one node by adding the current in the interaction calculation circuit in a period when the interaction signal enables the execution of the interaction, and
turns a current in the interaction calculation circuit OFF in a period when the interaction signal disables the execution of the interaction.

11. The information processing device according to claim 10 ,
wherein the processing of the ground state search for the plurality of units writes the value indicating the next state of the node determined in the interaction calculation circuit into the first memory cell based on the interaction signal.

12. The information processing device according to claim 9 ,
wherein the processing of the ground state search for the plurality of units limits a unit for updating the value indicating the state of the node based on the interaction signal.

13. The information processing device according to claim 12 ,
wherein the processing of the ground state search for the plurality of units prohibits simultaneous updating of an adjacent unit based on the interaction signal.

Assignees

• Hitachi Ltd

Inventors

• Yamaoka Masanao
• Oshima Takashi
• Hayashi Masato

Classifications

• G06F13/1652

  in a multiprocessor architecture (interprocessor communication using common memory G06F15/167) · CPC title

• G06N7/01

  Probabilistic graphical models, e.g. probabilistic networks · CPC title

• G11C11/16

  using elements in which the storage effect is based on magnetic spin effect · CPC title

• G11C2213/71

  Three dimensional array · CPC title

• G06F13/1668 Primary

  Details of memory controller · CPC title