Global bit line pre-charge circuit that compensates for process, operating voltage, and temperature variations

Patent metadata

Field	Value
Publication number	US-9390796-B2
Application number	US-201514790430-A
Country	US
Kind code	B2
Filing date	Jul 2, 2015
Priority date	Jun 10, 2011
Publication date	Jul 12, 2016
Grant date	Jul 12, 2016

Abstract

A memory array includes wordlines, local bitlines, two-terminal memory elements, global bitlines, and local-to-global bitline pass gates and gain stages. The memory elements are formed between the wordlines and local bitlines. Each local bitline is selectively coupled to an associated global bitline, by way of an associated local-to-global bitline pass gate. During a read operation when a memory element of a local bitline is selected to be read, a local-to-global gain stage is configured to amplify a signal on or passing through the local bitline to an amplified signal on or along an associated global bitline. The amplified signal, which in one embodiment is dependent on the resistive state of the selected memory element, is used to rapidly determine the memory state stored by the selected memory element. The global bit line and/or the selected local bit line can be biased to compensate for the Process Voltage Temperature (PVT) variation.

First claim

What is claimed is:

1. A non-volatile memory device, comprising:
a plurality of wordlines (WLs);
a plurality of local bitlines (LBLs) selectively electrically coupled with a plurality of global bit lines (GBLs);
a plurality of re-writable non-volatile two-terminal memory elements, each memory element positioned between a cross-point of one of the plurality of WLs with one of the plurality of LBLs and each memory element directly electrically in series with its respective WL and LBL; and
a plurality of amplifiers electrically coupled with the plurality of LBLs and the plurality of GBLs.

2. The device of claim 1 , wherein during a read operation an amplifier included in the plurality of amplifiers is configured to produce an amplified signal on or along a GBL associated with a selected re-writable non-volatile two-terminal memory element and a magnitude of the amplified signal is dependent upon a memory state of the selected re-writable non-volatile two-terminal memory element.

3. The device of claim 2 , wherein the magnitude of the amplified signal is dependent upon a resistive state of the selected re-writable non-volatile two-terminal memory element.

4. The device of claim 1 and further comprising:
a plurality of switching devices configured to selectively electrically couple LBLs included in the plurality of LBLs with GBLs included in the plurality of GBLs.

5. The device of claim 4 , wherein the plurality of switching devices comprises a plurality of pass gate transistors.

6. The device of claim 4 , wherein a switching device included in the plurality of switching devices is configured to couple an LBL to an associated GBL during times when a selected re-writable non-volatile two-terminal memory element associated with the LBL is being programmed or erased, and is configured to isolate the LBL from its associated GBL during times when the selected re-writable non-volatile two-terminal memory element is being read.

7. The device of claim 1 , wherein each re-writable non-volatile two-terminal memory element is configurable to two or more resistive states.

8. The device of claim 7 , wherein each re-writable non-volatile two-terminal memory element comprises at least one layer of a conductive metal oxide (CMO) including mobile oxygen and an insulating metal oxide (IMO) in contact with the CMO and having a thickness less than approximately 50 Angstroms.

9. The device of claim 1 , wherein the plurality of WLs, plurality of LBLs and plurality of re-writable non-volatile two-terminal memory elements are arranged in multiple WL layers, multiple LBL layers and multiple memory layers, respectively.

10. The device of claim 9 , wherein LBLs included in the plurality of LBLs are configured to extend through two or more memory layers and are associated with WL groups comprised of WLs of WL subgroups from two or more WL layers and re-writable non-volatile two-terminal memory elements from two or more memory layers.

11. The device of claim 9 , wherein the plurality of WLs, plurality of LBLs, and plurality of re-writable non-volatile two-terminal memory elements are configured in at least one two-terminal cross-point array.

12. The device of claim 1 , wherein the plurality of WLs, plurality of LBLs, and plurality of re-writable non-volatile two-terminal memory elements are configured in at least one two-terminal cross-point array.

13. The device of claim 1 , wherein a write operation to one or more of the plurality of re-writable non-volatile two-terminal memory elements does not require a prior erase operation.

14. A non-volatile memory, comprising:
a plurality of global bitlines (GBLs);
a cross-point memory array including a plurality of wordlines (WLs) and a plurality of memory array portions, each memory array portion being selectively electrically coupled with one of the plurality of GBLs, and each memory array portion including
a local bitline (LBL),
a plurality of re-writable non-volatile two-terminal memory elements positioned between a cross-point of the LBL and a word line (WL) of a WL group from the plurality of WLs, each memory element configured to store at least one bit of data, and
an amplifier electrically coupled with the LBL and an associated GBL; and

logic circuitry configured to perform data operations on one or more of the plurality of re-writable non-volatile two-terminal memory elements of the cross-point memory array.

15. The memory of claim 14 , wherein during a read operation the amplifier is configured to produce an amplified signal on or along the associated GBL and a magnitude of the amplified signal is dependent upon a memory state of a selected re-writable non-volatile two-terminal memory element.

16. The memory of claim 15 , wherein the magnitude of the amplified signal is dependent upon a resistive state of the selected re-writable non-volatile two-terminal memory element.

17. The memory of claim 14 , wherein each memory array portion further includes a switching device configured to couple an LBL of the memory array portion to an associated GBL during erase and program operations and isolate the LBL from the associated GBL during read operations.

18. The memory of claim 17 , wherein the switching device of the memory array portions comprises pass gate transistors.

19. The memory of claim 14 , wherein the cross-point memory array comprises a multi-layer memory array including a plurality of memory layers and a plurality of WL layers, and LBLs of the memory array portions are configured to extend through two or more memory layers.

20. The memory of claim 14 , wherein the plurality of re-writable non-volatile two-terminal memory elements are individually addressable for data operations on a basis of at least a single bit.

Assignees

• Unity Semiconductor Corp

Inventors

• Siau Chang Hua
• Bateman Bruce Lynn

Classifications

• G11C13/0069 Primary

  Writing or programming circuits or methods · CPC title

• G11C13/004 Primary

  Reading or sensing circuits or methods · CPC title

• G11C13/0026

  Bit-line or column circuits · CPC title

• G11C5/06

  Arrangements for interconnecting storage elements electrically, e.g. by wiring · CPC title

• G11C7/04

  with means for avoiding disturbances due to temperature effects · CPC title