Post driver

Patent metadata

Field	Value
Publication number	US-9325318-B1
Application number	US-201514743236-A
Country	US
Kind code	B1
Filing date	Jun 18, 2015
Priority date	Nov 26, 2014
Publication date	Apr 26, 2016
Grant date	Apr 26, 2016

Abstract

A post driver comprises a source follower and a first sub-unit. The source follower includes an input to receive a first voltage from a pad, and an output to provide a second voltage. The first sub-unit includes a first transistor and a second transistor. The first transistor is coupled between the pad and a first power rail, and is configured to operate in a sub-threshold region in response to the second voltage and a first range of the first voltage. The second transistor is coupled in parallel with the first transistor between the pad and the first power rail, and is configured to electrically connect the pad to the first power rail in response to a second range of the first voltage.

First claim

What is claimed is:

1. A post driver, comprising:
a source follower including an input to receive a first voltage from a pad, and an output to provide a second voltage; and
a first sub-unit, comprising:
a first transistor coupled between the pad and a first power rail, the first transistor configured to operate in a sub-threshold region in response to the second voltage and a first range of the first voltage; and
a second transistor coupled in parallel with the first transistor between the pad and the first power rail, the second transistor configured to electrically connect the pad to the first power rail in response to a second range of the first voltage.

2. The post driver of claim 1 , wherein the first transistor includes a gate coupled to the output, a drain coupled to the pad, and a source coupled via a third transistor to the first power rail, and wherein the second transistor includes a gate coupled to the pad, a drain coupled to the pad, and a source coupled via the third transistor to the first power rail.

3. The post driver of claim 2 further comprising a fourth transistor coupled between the third transistor and the first power rail, wherein the fourth transistor has a smaller aspect ratio than the third transistor.

4. The post driver of claim 1 , wherein the second transistor has a greater aspect ratio than the first transistor.

5. The post driver of claim 1 , wherein the source follower includes:
a resistive device connected between a second power rail and the output, the first and second power rails providing different voltages; and
a transistor including a gate coupled to the pad, a source coupled to the output, and a drain coupled to the second power rail.

6. The post driver of claim 5 , wherein the resistive device includes one of a resistor and a pass gate.

7. The post driver of claim 5 , wherein the first range of the first voltage ranges from −10% to 50% of the voltage level of the second power rail, and the second range of the first voltage ranges from 50% to 110% of the voltage level of the second power rail.

8. The post driver of claim 5 , wherein the first range of the first voltage ranges from 50% to 110% of the voltage level of the second power rail, and the second range of the first voltage ranges from −10% to 50% of the voltage level of the second power rail.

9. The post driver of claim 1 further comprising at least one second sub-unit coupled in parallel with the first sub-unit between the pad and the first power rail, wherein each of the at least one second sub-unit includes:
a first transistor coupled between the pad and the first power rail, the first transistor configured to operate in a sub-threshold region in response to the second voltage and the first range of the first voltage; and
a second transistor coupled in parallel with the first transistor between the pad and the first power rail, the second transistor configured to electrically connect the pad to the first power rail in response to a second range of the first voltage.

10. The post driver of claim 9 , wherein the first transistor in one of the at least one second sub-unit has a same aspect ratio as the first transistor in the first sub-unit.

11. The post driver of claim 9 , wherein the first transistor in one of the at least one second sub-unit has a different aspect ratio from the first transistor in the first sub-unit.

12. A post driver, comprising:
a first transistor coupled between a pad and a first power rail;
a first source follower configured to cause the first transistor to, in response to a first range of a voltage from the pad, operate in a sub-threshold region;
a second transistor coupled between the pad and a second power rail, the first and second power rails providing different voltages; and
a second source follower configured to cause the second transistor to, in response to a second range of the voltage from the pad, operate in a sub-threshold region.

13. The post driver of claim 12 further comprising a transistor coupled in parallel with the first transistor between the pad and the first power rail, the transistor configured to electrically connect the pad to the first power rail in response to the second range of the voltage from the pad.

14. The post driver of claim 13 , wherein the transistor has a greater aspect ratio than the first transistor.

15. The post driver of claim 12 further comprising a transistor coupled in parallel with the second transistor between the pad and the second power rail, the transistor configured to electrically connect the pad to the second power rail in response to the first range of the voltage from the pad.

16. The post driver of claim 15 , wherein the transistor has a greater aspect ratio than the second transistor.

17. The post driver of claim 12 , wherein each of the first and second source followers includes a resistive device selected from one of a resistor and a pass gate.

18. A method of operating a post driver, the method comprising:
providing a first transistor between a pad and a power rail;
providing a second transistor connected in parallel with the first transistor between the pad and the power rail;
providing a source follower including an input coupled to the pad and an output coupled to the first transistor;
electrically connecting the pad to the power rail in response to a first range of a voltage from the pad; and
electrically connecting the pad to the power rail via the second transistor in response to a second range of the voltage from the pad.

19. The method of claim 18 , wherein electrically connecting the pad to the power rail in response to a first range of a voltage from the pad includes:
clamping the first transistor to work in a sub-threshold region in response to the first range of the voltage received at the input from the pad.

20. The method of claim 18 , wherein the second transistor has a greater aspect ratio than the first transistor.

Assignees

• Taiwan Semiconductor Mfg

Inventors

• Huang Tien-Chien

Classifications

• H03K19/018557 Primary

  Coupling arrangements; Impedance matching circuits · CPC title

• H03K19/018507

  Interface arrangements · CPC title