Semiconductor device and electronic appliance

Patent metadata

Field	Value
Publication number	US-2016293129-A1
Application number	US-201615175189-A
Country	US
Kind code	A1
Filing date	Jun 7, 2016
Priority date	Sep 16, 2009
Publication date	Oct 6, 2016
Grant date	—

Abstract

The amplitude voltage of a signal input to a level shifter can be increased and then output by the level shifter circuit. Specifically, the amplitude voltage of the signal input to the level shifter can be increased to be output. This decreases the amplitude voltage of a circuit (a shift register circuit, a decoder circuit, or the like) which outputs the signal input to the level shifter. Consequently, power consumption of the circuit can be reduced. Alternatively, a voltage applied to a transistor included in the circuit can be reduced. This can suppress degradation of the transistor or damage to the transistor.

First claim

1 . (canceled)

2 . A semiconductor device comprising:
a first transistor; a second transistor; a third transistor; a fourth transistor; a fifth transistor; and a sixth transistor, wherein: a channel formation region of each of the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor and the sixth transistor includes an oxide semiconductor; one of a source and a drain of the first transistor is directly connected to one of a source and a drain of the second transistor; one of a source and a drain of the third transistor is directly connected to one of a source and a drain of the fourth transistor; one of a source and a drain of the fifth transistor is directly connected to one of a source and a drain of the sixth transistor; a gate of the first transistor is directly connected to the one of the source and the drain of the third transistor; a gate of the second transistor is directly connected to a gate of the fourth transistor; the gate of the second transistor is directly connected to the one of the source and the drain of the fifth transistor; a gate of the third transistor is directly connected to a gate of the sixth transistor; a gate of the fifth transistor is directly connected to the other of the source and the drain of the fifth transistor; the other of the source and the drain of the second transistor is directly connected to the other of the source and the drain of the fourth transistor; the other of the source and the drain of the second transistor is directly connected to the other of the source and the drain of the sixth transistor; a clock signal is inputted to the other of the source and the drain of the fifth transistor; a first signal is inputted to the gate of the third transistor; and a second signal is outputted from the one of the source and the drain of the first transistor.

3 . A semiconductor device comprising:
a first transistor; a second transistor; a third transistor; a fourth transistor; a fifth transistor; a sixth transistor; a seventh transistor; an eighth transistor; a ninth transistor; a tenth transistor; an eleventh transistor; and a twelfth transistor, wherein: a channel formation region of each of the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor, the ninth transistor, the tenth transistor, the eleventh transistor and the twelfth transistor includes an oxide semiconductor; one of a source and a drain of the first transistor is directly connected to one of a source and a drain of the second transistor; one of a source and a drain of the third transistor is directly connected to one of a source and a drain of the fourth transistor; one of a source and a drain of the fifth transistor is directly connected to one of a source and a drain of the sixth transistor; a gate of the first transistor is directly connected to the one of the source and the drain of the third transistor; a gate of the second transistor is directly connected to a gate of the fourth transistor; the gate of the second transistor is directly connected to the one of the source and the drain of the fifth transistor; a gate of the third transistor is directly connected to a gate of the sixth transistor; a gate of the fifth transistor is directly connected to the other of the source and the drain of the fifth transistor; one of a source and a drain of the seventh transistor is directly connected to one of a source and a drain of the eighth transistor; one of a source and a drain of the ninth transistor is directly connected to one of a source and a drain of the tenth transistor; one of a source and a drain of the eleventh transistor is directly connected to one of a source and a drain of the twelfth transistor; a gate of the seventh transistor is directly connected to the one of the source and the drain of the ninth transistor; a gate of the eighth transistor is directly connected to a gate of the tenth transistor; the gate of the eighth transistor is directly connected to the one of the source and the drain of the eleventh transistor; a gate of the ninth transistor is directly connected to a gate of the twelfth transistor; a gate of the eleventh transistor is directly connected to the other of the source and the drain of the eleventh transistor; the other of the source and the drain of the second transistor is directly connected to the other of the source and the drain of the fourth transistor; the other of the source and the drain of the second transistor is directly connected to the other of the source and the drain of the sixth transistor; the other of the source and the drain of the second transistor is directly connected to the other of the source and the drain of the eighth transistor; the other of the source and the drain of the second transistor is directly connected to the other of the source and the drain of the tenth transistor; the other of the source and the drain of the second transistor is directly connected to the other of the source and the drain of the twelfth transistor; a first clock signal is inputted to the other of the source and the drain of the fifth transistor; a second clock signal is inputted to the other of the source and the drain of the eleventh transistor; a first signal is inputted to the gate of the third transistor; a second signal is outputted from the one of the source and the drain of the first transistor; a third signal is inputted to the gate of the ninth transistor; and a fourth signal is outputted from the one of the source and the drain of the seventh transistor.

4 . A semiconductor device comprising:
a first transistor; a second transistor; a third transistor; a fourth transistor; a fifth transistor; and a sixth transistor, wherein: a channel formation region of each of the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor and the sixth transistor includes an oxide semiconductor; a channel width of the first transistor is larger than a channel width of the second transistor, the channel width of the first transistor is larger than a channel width of the third transistor, the channel width of the first transistor is larger than a channel width of the fourth transistor, the channel width of the first transistor is larger than a channel width of the fifth transistor, the channel width of the first transistor is larger than a channel width of the sixth transistor, the channel width of the second transistor is larger than the channel width of the third transistor, the channel width of the second transistor is larger than the channel width of the fifth transistor, the channel width of the second transistor is larger than the channel width of the sixth transistor, one of a source and a drain of the first transistor is directly connected to one of a source and a drain of the second transistor; one of a source and a drain of the third transistor is directly connected to one of a source and a drain of the fourth transistor; one of a source and a drain of the fifth transistor is directly connected to one of a source and a drain of the sixth transistor; a gate of the first transistor is directly connected to the one of the source and the drain of the third transistor; a gate of the second transistor is directly connected to a gate of the fourth transistor; the gate of the second transistor is directly connected to the one of the source and the drain of the fifth transistor; a gate of the third transistor is directly connected to a gate of the sixth transistor; a gate of the fifth transistor is directly connected to the other of the source and the drain

Assignees

• Semiconductor Energy Lab

Inventors

• Koyama Jun
• Umezaki Atsushi

Classifications

• H03K19/018557

  Coupling arrangements; Impedance matching circuits · CPC title

• G09G3/3677 Primary

  suitable for active matrices only · CPC title

• G09G2310/0251

  Precharge or discharge of pixel before applying new pixel voltage · CPC title

• H03K17/687 Primary

  the devices being field-effect transistors · CPC title

• H03K19/0013

  in field effect transistor circuits · CPC title