Spin transfer torque cell for magnetic random access memory

Patent metadata

Field	Value
Publication number	US-9318698-B2
Application number	US-201514699716-A
Country	US
Kind code	B2
Filing date	Apr 29, 2015
Priority date	Jun 24, 2011
Publication date	Apr 19, 2016
Grant date	Apr 19, 2016

Abstract

Embodiments are directed to STT MRAM devices. One embodiment of an STT MRAM device includes a reference layer, a tunnel barrier layer, a free layer and one or more conductive vias. The reference layer is configured to have a fixed magnetic moment. In addition, the tunnel barrier layer is configured to enable electrons to tunnel between the reference layer and the free layer through the tunnel barrier layer. The free layer is disposed beneath the tunnel barrier layer and is configured to have an adaptable magnetic moment for the storage of data. The conductive via is disposed beneath the free layer and is connected to an electrode. Further, the conductive via has a width that is smaller than a width of the free layer such that a width of an active STT area for the storage of data in the free layer is defined by the width of the conductive via.

First claim

What is claimed is:

1. A method for manufacturing spin transfer torque (STT) magnetic random access memory (MRAM) device comprising:
forming at least one conductive via on at least one first electrode;
depositing over the at least one conductive via a magnetic tunnel junction stack such that a free layer that is configured to have an adaptable magnetic moment for storage of data is disposed between the at least one conductive via and a tunnel barrier layer that is configured to enable electrons to tunnel between the free layer and a reference layer through the tunnel barrier layer; and
depositing at least one second electrode over the magnetic tunnel junction stack to generate an MRAM device structure.

2. The method of claim 1 , further comprising
adding an insulator between the free layer and the electrode such that the at least one conductive via is disposed laterally to the first insulator; and
depositing a material between the first insulator and the free layer.

3. The method of claim 2 , further comprising:
applying a chemical-mechanical planarization process on a surface of the at least one conductive via.

4. The method of claim 2 , wherein the material includes at least one excess agent selected from the group consisting of elements from the thirteenth, fifteenth, sixteenth and seventeenth columns of the periodic table of elements.

5. The method of claim 2 , further comprising:
annealing the MRAM device structure to cause the material to react with the free layer to increase the resistivity of portions of the free layer that are above the material.

6. The method of claim 5 , wherein the annealing transforms the portions of the free layer that are above the material to be non-conductive and non-magnetic.

7. The method of claim 5 , wherein the annealing is performed at a first temperature between 200° C. and 450° C. and wherein the depositing the material is performed at a second temperature that is lower than the first temperature.

8. The method of claim 1 , wherein the free layer includes an excess agent and wherein the method further comprises:
annealing the MRAM device structure to cause the at least one conductive via to absorb the excess agent and to increase the conductivity of a portion of the free layer that is above the at least one conductive via.

9. The method of claim 1 , further comprising:
etching through the magnetic tunnel junction stack to generate a plurality of cells such that each of the conductive vias is included in a different cell and each of the cells is defined by a separate pillar, wherein each of the pillars includes a separate stack of the reference layer, the tunnel barrier layer and the free layer.

10. The method of claim 1 , wherein the depositing the magnetic tunnel junction stack comprises depositing the free layer directly on the at least one conductive via.

Assignees

• IBM

Inventors

• Gaidis Michael C
• Nowak Janusz J
• Worledge Daniel C

Classifications

• H01F10/3254 Primary

  the spacer being semiconducting or insulating, e.g. for spin tunnel junction [STJ] · CPC title

• B82Y40/00

  Manufacture or treatment of nanostructures · CPC title

• H01F10/329

  Spin-exchange coupled multilayers wherein the magnetisation of the free layer is switched by a spin-polarised current, e.g. spin torque effect · CPC title

• H01F41/307

  insulating or semiconductive spacer · CPC title

• H01L43/12 Primary

  Electricity · mapped topic