Memory arrays, semiconductor constructions, and methods of forming semiconductor constructions

Patent metadata

Field	Value
Publication number	US-9318493-B2
Application number	US-201414502978-A
Country	US
Kind code	B2
Filing date	Sep 30, 2014
Priority date	May 27, 2011
Publication date	Apr 19, 2016
Grant date	Apr 19, 2016

Abstract

Some embodiments include memory arrays. The memory arrays may have digit lines under vertically-oriented transistors, with the digit lines interconnecting transistors along columns of the array. Each individual transistor may be directly over only a single digit line, with the single digit line being entirely composed of one or more metal-containing materials. The digit lines can be over a deck, and electrically insulative regions can be directly between the digit lines and the deck. Some embodiments include methods of forming memory arrays. A plurality of linear segments of silicon-containing material may be formed to extend upwardly from a base of the silicon-containing material. The base may be etched to form silicon-containing footings under the linear segments, and the footings may be converted into metal silicide. The linear segments may be patterned into a plurality of vertically-oriented transistor pedestals that extend upwardly from the metal silicide footings.

First claim

We claim:

1. A semiconductor construction, comprising:
an array of vertically-oriented transistors; individual of the transistors comprising a bottom source/drain region, a top source/drain region, and a channel region between the top and bottom source/drain regions; the array comprising rows and columns;
access lines extending along rows of the array to interconnect transistors along said rows, the access lines extending across the channel regions and forming gates across the transistors to gatedly couple the top and bottom source/drain regions through the channel regions;
digit lines extending along columns of the array to interconnect transistors along said columns, the digit lines being electrically coupled to the bottom source/drain regions of the transistors and being comprised entirely of one or more metal-containing materials;
each transistor of the array being uniquely addressed by a combination of an access line and a digit line; and
wherein the digit lines directly contact semiconductor material of a deck directly under the digit lines; the semiconductor material directly under the digit lines being first doped stripes doped to a first dopant type; the semiconductor construction further comprising second doped stripes directly between the first doped stripes and doped to a second dopant type opposite to the first dopant type.

2. The semiconductor construction of claim 1 wherein the first and second dopant types are n-type and p-type respectively.

3. The semiconductor construction of claim 1 wherein the first and second dopant types are p-type and n-type respectively.

4. The semiconductor construction of claim 1 further comprising metal/semiconductor material directly against the bottom source/drain regions; and wherein the digit lines comprise a metal-containing composition directly against the metal/semiconductor material.

5. The semiconductor construction of claim 4 wherein the metal/semiconductor material is metal silicide.

6. The semiconductor construction of claim 4 wherein the metal/semiconductor material is metal germanide.

7. The semiconductor construction of claim 4 wherein the metal/semiconductor material is configured as lines that are part of the digit lines.

8. The semiconductor construction of claim 4 wherein the metal/semiconductor material is configured as separated blocks associated with the individual transistors.

9. The semiconductor construction of claim 4 wherein the metal-containing composition comprises metal nitride, elemental metal, or mixtures of two or more metals.

10. The semiconductor construction of claim 1 further comprising metal/semiconductor material directly against the bottom source/drain regions; wherein the digit lines comprise a titanium-containing composition directly against the metal/semiconductor material, and wherein titanium nitride is directly against the titanium-containing composition; the titanium-containing composition and titanium nitride both extending into cavities within the metal/semiconductor material and extending to under the bottom source/drain regions of the transistors.

Assignees

• Micron Technology Inc

Inventors

• Heineck Lars P
• Surthi Shyam
• Guha Jaydip

Classifications

• H10D64/01328

  by defining the conductor using a sidewall spacer mask, a transformation under a mask or a plating at a sidewall · CPC title

• H10D30/63

  Vertical IGFETs (H10D30/66 {, H10D30/6728, H10D30/689, H10D30/693} take precedence) · CPC title

• H10D30/711 Primary

  having floating bodies · CPC title

• H10D30/477

  Vertical HEMTs or vertical HHMTs · CPC title

• H10D30/025

  of vertical IGFETs (of VDMOS H10D30/0291; of vertical TFTs H10D30/0318) · CPC title