Evaluating transistors with e-beam inspection

Patent metadata

Field	Value
Publication number	US-9291665-B2
Application number	US-201213470645-A
Country	US
Kind code	B2
Filing date	May 14, 2012
Priority date	May 14, 2012
Publication date	Mar 22, 2016
Grant date	Mar 22, 2016

Abstract

A test structure of a semiconductor wafer includes a series of electrical units connected electrically in series output-to-input in an open loop configuration. The series of electrical units is configured to have alternating output voltages, such that each electrical unit is configured to output a voltage opposite an output voltage of a preceding electrical unit. Each electrical unit is configured to have an output voltage that alternates when an input voltage applied to a first electrical unit in the series of electrical units alternates.

First claim

What is claimed is:

1. A test structure of a semiconductor wafer, the test structure comprising:
a series of electrical units connected electrically in series output-to-input in an open loop configuration, the series of electrical units configured to have alternating output voltages, such that each electrical unit is configured to output a voltage opposite an output voltage of a preceding electrical unit, and such that each electrical unit is configured to have an output voltage that alternates when an input voltage applied to a first electrical unit in the series of electrical units alternates,
wherein the series of electrical units is a series of latches, and
wherein each latch of the series of latches comprises two pairs of cross-coupled FETs, wherein a gate of a first pair of the FETs is connected to a drain-to-drain connection of the second pair of the FETs, and a gate of the second pair of the FETs is connected to a drain-to-drain connection of the first pair of the FETs.

2. The test structure of claim 1 , wherein the series of electrical units is a series of inverters, each inverter comprising a pair of field effect transistors (FETs) connected drain-to-drain.

3. The test structure of claim 1 , wherein the test structure is formed by a metal layer on the semiconductor wafer having no intervening metal layers between the metal layer and a substrate of the semiconductor wafer.

4. The test structure of claim 1 , wherein each latch further includes an input latch configured to receive an input voltage at a source and having a drain connected to the drain-to-drain connection of the first pair of FETs, and having a gate connected to a power line, and each latch further includes an output FET having source connected to the drain-to-drain connection of the second pair of FETs, a drain connected to a source of an input FET of a next latch in the series of latches, and a gate connected to the power line.

5. The test structure of claim 4 , wherein the FETs include positive field effect transistors (PFETs) and negative field effect transistors (NFETs), and the structure has an equal number of PFETs and NFETs.

6. The structure of claim 1 , wherein a number of the electrical units is at least 100.

7. The test structure of claim 1 , wherein a first electrical unit in the series of electrical units is connected to at least one of a pad configured to receive a probe to provide an input voltage to the series of electrical units and a capacitor configured to generate the input voltage upon being irradiated by one of an optical beam and an electron beam.

8. A method, comprising:
applying a voltage to a test structure comprising a plurality of electrical units connected in series output-to-input, each of the plurality of electrical units configured to output a voltage at a level opposite a voltage level of a preceding electrical unit of the plurality of electrical units connected in series; and
determining whether a fault exists in the test structure by generating an e-beam image of the test structure and analyzing output voltages of the plurality of electrical units in the e-beam image to determine whether output voltages of two consecutive electrical units are the same,
wherein determining whether the fault exists in the test structure includes analyzing the output voltages of the plurality of electrical units in the e-beam image a first time when a high voltage is applied to an input of the test structure and a second time when a low voltage is applied to an input of the test structure.

9. The method of claim 8 , wherein generating the e-beam image includes generating a voltage-contrast image, and
determining whether the fault exists in the test structure includes determining whether the two consecutive electrical units have a same shade of lightness or darkness.

10. The method of claim 8 , wherein the e-beam image simultaneously displays each of the plurality of electrical units, and
analyzing the output voltages of the plurality of electrical units in the e-beam image includes simultaneously analyzing each of the plurality of electrical units displayed in the e-beam image.

11. The method of claim 8 , wherein applying the voltage to the test structure includes charging a capacitor connected to the test structure to provide the voltage to the metal layer.

12. The method of claim 11 , wherein charging the capacitor includes directing a laser beam at the capacitor.

13. The method of claim 8 , wherein applying the voltage to the test structure includes applying a voltage probe to an input voltage pad connected to an input of a first electrical unit of the plurality of electrical units connected in the series, the first electrical unit being an electrical unit at an end-most position of the plurality of electrical units connected in the series.

14. The method of claim 8 , wherein the test structure is formed by a first metal layer located on a semiconductor substrate, such that no metal layer is located between the first metal layer and the semiconductor substrate.

15. The method of claim 8 , wherein the first metal layer includes portions of at least one static random access memory (SRAM) circuit, and
the method further comprises:
forming at least one additional metal layer to complete the at least one SRAM circuit upon determining that no fault exists in the test structure.

16. A system, comprising:
a test structure of a semiconductor chip, the test structure including a series of electrical units connected output-to-input, the series of electrical units configured to have alternating output voltages, such that each electrical unit is configured to output a voltage opposite an output voltage of a preceding electrical unit and such that each electrical unit is configured to have an output voltage that alternates when an input voltage applied to a first electrical unit in the series of electrical units alternates;
an e-beam assembly configured to direct an e-beam at a test structure to detect voltage levels at outputs of the electrical units; and
an analysis unit configured to detect whether a faulty electrical unit exists in the test structure by analyzing an image generated by the e-beam assembly,
wherein the e-beam assembly is configured to apply an input voltage to a first electrical unit in the series of electrical units by applying radiation to a capacitor connected to a voltage input of the first electrical unit.

17. The system of claim 16 , wherein the analysis unit is configured to detect a faulty electrical unit by detecting whether outputs of two consecutive electrical units have a same shade in the e-beam image.

18. The system of claim 16 , wherein the e-beam assembly is configured to apply an input voltage to a first electrical unit in the series of electrical units by applying a voltage probe to a pad connected to an input of the first electrical unit, wherein the first electrical unit is an electrical unit at an upstream-most end of the series of electrical units.

19. The system of claim 16 , wherein the e-beam assembly is configured to generate first and second e-beams,
the e-beam assembly is configured to direct the first e-beam at the electrical units at the test structure to detect the voltage levels at the outputs of the electrical units, and
the e-beam assembly is configured to direct the second e-beam at the capacitor connected to the voltage input of the first electrical unit to generate the input voltage.

20. The system of claim 16 , wherein the radiation is a laser beam.

21. Th

Assignees

• Patterson Oliver D
• Song Zhigang
• Globalfoundries Inc

Inventors

• Patterson Oliver D
• Song Zhigang

Classifications

• G01R31/2653 Primary

  using electron beams · CPC title

• G01R31/275

  for testing individual semiconductor components within integrated circuits · CPC title

• G01R31/31721

  Power aspects, e.g. power supplies for test circuits, power saving during test (for scan test G01R31/318575) · CPC title