Double layer release temporary bond and debond processes and systems
US-10224229-B2 · Mar 5, 2019 · US
US10345373B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-10345373-B2 |
| Application number | US-201715720839-A |
| Country | US |
| Kind code | B2 |
| Filing date | Sep 29, 2017 |
| Priority date | Sep 29, 2017 |
| Publication date | Jul 9, 2019 |
| Grant date | Jul 9, 2019 |
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A method for inspecting a semiconductor device structure is provided. The method includes receiving a semiconductor device structure having a to-be-inspected feature. The semiconductor device structure has a first surface and a second surface. The method also includes applying a polymer-containing solution over the first surface of the semiconductor device structure. The method further includes disposing a transparent substrate over the first surface of the semiconductor device structure and the polymer-containing solution. In addition, the method includes irradiating the polymer-containing solution with a light to form an adhesive layer between the transparent substrate and the semiconductor device structure. The adhesive layer bonds the transparent substrate and the semiconductor device structure. The method also includes inspecting the to-be-inspected feature.
Opening claim text (preview).
What is claimed is: 1. A method for inspecting a semiconductor device structure, comprising: receiving a semiconductor device structure comprising a to-be-inspected feature, wherein the semiconductor device structure has a first surface and a second surface; applying a polymer-containing solution over the first surface of the semiconductor device structure; disposing a transparent substrate over the first surface of the semiconductor device structure and the polymer-containing solution; irradiating the polymer-containing solution with a light to form an adhesive layer between the transparent substrate and the semiconductor device structure, wherein the adhesive layer bonds the transparent substrate and the semiconductor device structure; and inspecting the to-be-inspected feature. 2. The method for inspecting a semiconductor device structure as claimed in claim 1 , further comprising partially removing the semiconductor device structure from the second surface to form an opening extending towards the to-be-inspected feature, wherein the to-be-inspected feature is inspected after or during the formation of the opening. 3. The method for inspecting a semiconductor device structure as claimed in claim 2 , wherein the opening is formed using an energy beam. 4. The method for inspecting a semiconductor device structure as claimed in claim 2 , wherein the opening is formed using a mechanical drilling process. 5. The method for inspecting a semiconductor device structure as claimed in claim 1 , wherein the polymer-containing solution comprises an ultraviolet light curable epoxy resin. 6. The method for inspecting a semiconductor device structure as claimed in claim 1 , wherein the light has a wavelength, and the wavelength is in a range from about 300 nm to about 400 nm. 7. The method for inspecting a semiconductor device structure as claimed in claim 6 , further comprising using a filter element to filter out infrared light and visible light while irradiating the polymer-containing solution with the light. 8. The method for inspecting a semiconductor device structure as claimed in claim 1 , further comprising thinning the semiconductor device structure from the first surface before applying the polymer-containing solution. 9. The method for inspecting a semiconductor device structure as claimed in claim 8 , further comprising: inspecting the semiconductor device structure after thinning the semiconductor device structure to locate a target region where the to-be-inspected feature is positioned; and thinning the target region before applying the polymer-containing solution. 10. The method for inspecting a semiconductor device structure as claimed in claim 9 , wherein the polymer-containing solution is applied on the target region after the target region is thinned. 11. The method for inspecting a semiconductor device structure as claimed in claim 1 , wherein the to-be-inspected feature is inspected using an electron microscope. 12. A method for inspecting a semiconductor device structure, comprising: receiving a chip package comprising a to-be-inspected feature, wherein the chip package has a first surface and a second surface; applying a polymer-containing solution over the first surface of the chip package; disposing a carrier substrate over the first surface of the chip package such that the polymer-containing solution spreads between the carrier substrate and the chip package; irradiating the polymer-containing solution with a light to transform the polymer-containing solution into an adhesive layer bonding the carrier substrate and the chip package; partially removing the chip package from the second surface to form an opening extending towards the to-be-inspected feature; and inspecting the to-be-inspected feature after or during the formation of the opening. 13. The method for inspecting a semiconductor device structure as claimed in claim 12 , wherein the chip package is partially removed layer by layer using an energy beam during the formation of the opening until the to-be-inspected feature is observed by an electron microscope. 14. The method for inspecting a semiconductor device structure as claimed in claim 12 , further comprising thinning the chip package from the first surface before applying the polymer-containing solution. 15. The method for inspecting a semiconductor device structure as claimed in claim 14 , further comprising: inspecting the chip package after thinning the chip package to locate a target region where the to-be-inspected feature is positioned; and marking the target region before applying the polymer-containing solution. 16. The method for inspecting a semiconductor device structure as claimed in claim 14 , wherein a semiconductor die of the chip package is thinned during the thinning of the chip package, and the to-be-inspected feature is positioned in the semiconductor die. 17. A method for inspecting a semiconductor device structure, comprising: receiving a semiconductor device structure comprising a to-be-inspected feature, wherein the semiconductor device structure has a first surface and a second surface; identifying a target region of the semiconductor device structure, wherein the to-be-inspected feature is in the target region; dispensing one or more droplets of a polymer-containing solution over the target region; disposing a transparent substrate over the semiconductor device structure such that the polymer-containing solution spreads between the transparent substrate and the chip package; irradiating the polymer-containing solution with an ultraviolet light to cure the polymer-containing solution such that an adhesive layer bonding the transparent substrate and the semiconductor device structure is formed; forming an opening extending from the second surface of the semiconductor device structure towards the to-be-inspected feature; and inspecting the to-be-inspected feature after or during the formation of the opening. 18. The method for inspecting a semiconductor device structure as claimed in claim 17 , further comprising thinning the semiconductor device structure before the target region is identified, wherein the target region is identified using an infrared light. 19. The method for inspecting a semiconductor device structure as claimed in claim 17 , further comprising thinning the target region using a mechanical drilling process before applying the polymer-containing solution. 20. The method for inspecting a semiconductor device structure as claimed in claim 17 , wherein the formation of the opening and the inspecting of the to-be-inspected feature are performed in a same vacuum chamber.
comprising optical enhancement of defects or not-directly-visible states · CPC title
Structural properties, e.g. testing or measuring thicknesses, line widths, warpage, bond strengths or physical defects · CPC title
using non-ionising electromagnetic radiation, e.g. optical radiation · CPC title
of integrated circuits · CPC title
of integrated circuits (G01R31/305 - G01R31/315 take precedence) · CPC title
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