Printed circuit board and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-9288903-B2
Application number	US-201113094941-A
Country	US
Kind code	B2
Filing date	Apr 27, 2011
Priority date	Jul 30, 2010
Publication date	Mar 15, 2016
Grant date	Mar 15, 2016

Abstract

A plurality of conductor traces are formed on a porous base insulating layer made of porous ePTFE. Each conductor trace has a laminated structure of a seed layer and a conductor layer. A cover insulating layer is formed on the base insulating layer to cover each conductor trace. The ePTFE used as the porous base insulating layer has continuous pores. An average pore size of the ePTFE is not less than 0.05 μm and not more than 1.0 μm.

First claim

We claim:

1. A method of manufacturing a printed circuit board comprising the steps of:
preparing an insulating layer consisting essentially of a porous polytetrafluoroethylene having continuous pores, an average pore size of the continuous pores of said polytetrafluoroethylene being not more than 0.1 μm; and
forming a conductor pattern having a given pattern on said insulating layer using a processing solution such that the processing solution is prevented from entering or remaining in the continuous pores of said insulating layer.

2. The method of claim 1 , wherein the processing solution includes a developing solution, and
wherein said step of forming the conductor pattern comprises:
forming a resist film;
exposing the resist film in a given pattern; and
forming a plating resist by developing the resist film using the developing solution, such that the developing solution is prevented from entering or remaining in the continuous pores of said insulating layer.

3. The method of claim 2 , wherein the processing solution includes a plating solution, and
wherein said step of forming the conductor pattern further comprises forming the conductor pattern using the plating solution except for in a region of the plating resist, such that the plating solution is prevented from entering or remaining in the continuous pores of said insulating layer.

4. The method of claim 3 , wherein the processing solution includes a stripping solution, and
wherein said step of forming the conductor pattern further comprises removing the plating resist using the stripping solution, such that the stripping solution is prevented from entering or remaining in the continuous pores of said insulating layer.

5. The method of claim 2 , wherein the processing solution includes a smoothing solution, and
wherein said step of forming the resist film comprises:
forming a seed layer on said insulating layer;
smoothing the seed layer using the smoothing solution, such that the smoothing solution is prevented from entering or remaining in the continuous pores of said insulating layer; and
forming the resist film on the seed layer.

6. The method of claim 5 , wherein the processing solution includes an etching solution, and
wherein a step of stripping the plating resist comprises removing the seed layer by etching using the etching solution, such that the etching solution is prevented from entering or remaining in the continuous pores of said insulating layer.

7. The method of claim 1 , wherein the processing solution includes a plating solution, and
wherein said step of forming the conductor pattern comprises forming by a conductor layer using the plating solution, such that the plating solution is prevented from entering or remaining in the continuous pores of said insulating layer.

8. The method of claim 7 , wherein the processing solution includes a developing solution, and
wherein said step of forming the conductor pattern further comprises:
forming a resist film on the conductor layer;
exposing the resist film in a given pattern; and
forming an etching resist by developing the resist film using the developing solution, such that the developing solution is prevented from entering or remaining in the continuous pores of said insulating layer.

9. The method of claim 8 , wherein the processing solution includes an etching solution, and
wherein said step of forming the conductor pattern further comprises removing a region of the conductor layer by etching using the etching solution except for the etching resist, such that the etching solution is prevented from entering or remaining in the continuous pores of said insulating layer.

10. The method of claim 9 , wherein the processing solution includes a stripping solution, and
wherein said step of forming the conductor pattern further comprises removing the etching resist by stripping using the stripping solution, such that the stripping solution is prevented from entering or remaining in the continuous pores of said insulating layer.

11. The method of claim 7 , wherein the processing solution includes a smoothing solution, and
wherein said step of forming the conductor layer comprises smoothing the conductor layer using the smoothing solution, such that the smoothing solution is prevented from entering or remaining in the continuous pores of said insulating layer.

12. The method of claim 1 , wherein said polytetrafluoroethylene is expanded polytetrafluoroethylene.

Assignees

• Hasegawa Mineyoshi
• Okumura Keisuke
• Inoue Shinichi
• Hanazono Hiroyuki
• Nitto Denko Corp

Inventors

• Hasegawa Mineyoshi
• Okumura Keisuke
• Inoue Shinichi
• Hanazono Hiroyuki

Classifications

• H05K1/0393

  Flexible materials (H05K1/038 takes precedence; specific organic compositions are classified in H05K1/0313 and subgroups) · CPC title

• H05K3/108

  by semi-additive methods; masks therefor (characterised by metallic etch mask H05K3/062; electroplating methods or apparatus H05K3/241) · CPC title

• H05K2201/0116

  Porous, e.g. foam · CPC title

• H05K3/06

  the conductive material being removed chemically or electrolytically, e.g. by photo-etch process {(semi-additive methods H05K3/108)} · CPC title

• H05K3/28

  Applying non-metallic protective coatings {(H05K3/0091 takes precedence; methods for intermediate insulating layers for build-up multilayer circuits H05K3/4673)} · CPC title