Fused booth encoder multiplexer

Patent metadata

Field	Value
Publication number	US-9274751-B2
Application number	US-77645407-A
Country	US
Kind code	B2
Filing date	Jul 11, 2007
Priority date	Sep 30, 2003
Publication date	Mar 1, 2016
Grant date	Mar 1, 2016

Abstract

A multiplier circuit comprises a fused Booth encoder multiplexer which produces partial product bits, a tree which uses the partial product bits to generate partial products, and an adder which uses the partial products to generate intermediate sum and carry results for a multiplication operation. The fused Booth encoder multiplexer utilizes encoder-selector cells having a logic tree which carries out a Boolean function according to a Booth encoding and selection algorithm to produce one of the partial product bits at a dynamic node, and a latch connected to the dynamic node which maintains the value at an output node. The encoder-selector cells operate in parallel to produce the partial product bits generally simultaneously. A given one of the encoder-selector cells has a unique set of both multiplier operand inputs and multiplicand operand inputs, and produces a single partial product bit.

First claim

What is claimed is:

1. A fused Booth encoder multiplexer logic cell comprising:
a logic circuit having a plurality of operand input bits including multiplier input bits and multiplicand input bits, a dynamic node, a clock input, a logic tree containing a plurality of logic transistors, each logic transistor in said logic tree having a gate connected to one of the operand input bits and said logic transistors being interconnected to carry out a Boolean function according to a Booth encoding and selection algorithm to produce a partial product bit for a multiplication operation at the dynamic node in a single clock phase, a power transistor coupling said logic tree to a voltage source, said power transistor being controlled by said clock input, a foot transistor coupling said logic tree to electrical ground, said foot transistor being controlled by said clock input, and a latch connected to said dynamic node which maintains the partial product bit at an output node, said latch being controlled by said clock input, wherein said latch includes:
a first P-MOS transistor having a gate connected to said dynamic node, a source connected to said voltage source, and a drain;
a second P-MOS transistor having a gate, a source connected to said voltage source, and a drain connected to said drain of said first P-MOS transistor;
a first N-MOS transistor having a gate connected to said dynamic node, a source connected to said drains of said first and second P-MOS transistors, and a drain;
a second N-MOS transistor having a gate connected to said clock input, a source connected to said drain of said first N-MOS transistor, and a drain connected to electrical ground;
a third N-MOS transistor having a gate, a source connected to said drain of said first N-MOS transistor, and a drain connected to electrical ground; and
an inverter having an input connected to said drains of said first and second P-MOS transistors, and an output connected to said gates of said first P-MOS transistor and said third N-MOS transistor, said inverter output being further connected to said output node to produce an inverted value;
wherein said first P-MOS transistor and said first N-MOS transistor invert the value from the dynamic node, and the Boolean function of said logic tree accounts for inversion of the value by said first P-MOS transistor and said first N-MOS transistor.

2. A fused Booth encoder multiplexer utilizing a plurality of fused Booth encoder multiplexer logic cells according to claim 1 , wherein:
the logic cells are arranged in a two-dimensional array on an integrated circuit and operate in parallel to produce a respective plurality of partial product bits; and
a given one of the logic cells has a unique set of multiplicand and multiplier input bits.

3. The fused Booth encoder multiplexer logic cell of claim 1 wherein:
the operand inputs bits include two multiplicand input bits A(i . . . i+1) and three multiplier input bits C(i−1 . . . i+1); and
the Boolean function which produces the partial product bit is given by the expression
S =( A ( i )⊕ C ( i− 1))·( C ( i )⊕ C ( i− 1))+ A ( i+ 1)· C ( i− 1) ·C ( i )· C ( i+ 1)+ A ( i+ 1) · C ( i− 1)· C ( i ) · C ( i+ 1) .

4. The fused Booth encoder multiplexer logic cell of claim 1 wherein said logic tree includes a plurality of transistor stacks, each transistor stack having a plurality of said logic transistors serially connected source-to-drain, with one logic transistor in each stack having a source connected to said drain of power transistor and said dynamic node, and another logic transistor in each stack having a drain connected to said source of said foot transistor.

5. The fused Booth encoder multiplexer logic cell of claim 4 wherein a first source/drain junction in a first one of said transistor stacks is connected to a second source/drain junction in a second one of said transistor stacks.

Assignees

• Belluomini Wendy Ann
• Ngo Hung Cai
• Sawada Jun
• IBM

Inventors

• Belluomini Wendy Ann
• Ngo Hung Cai
• Sawada Jun

Classifications

• G06F7/533

  Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even · CPC title

• G06F7/5443

  Sum of products (for applications thereof, see the relevant places, e.g. G06F17/10, H03H17/00) · CPC title

• G06F2207/3872

  Precharge of output to prevent leakage · CPC title

• G06F7/5338 Primary

  each bitgroup having two new bits, e.g. 2nd order MBA · CPC title

• G06F7/483

  Computations with numbers represented by a non-linear combination of denominational numbers, e.g. rational numbers, logarithmic number system or floating-point numbers {(G06F7/4806, G06F7/4824, G06F7/49, G06F7/491, G06F7/544 take precedence)} · CPC title