Binary fused multiply-add floating-point calculations

Patent metadata

Field	Value
Publication number	US-9959093-B2
Application number	US-201615197290-A
Country	US
Kind code	B2
Filing date	Jun 29, 2016
Priority date	Feb 1, 2016
Publication date	May 1, 2018
Grant date	May 1, 2018

Abstract

A binary fused multiply-add floating-point unit configured to operate on an addend, a multiplier, and a multiplicand. The unit is configured to receive as the addend an unrounded result of a prior operation executed in the unit via an early result feedback path; to perform an alignment shift of the unrounded addend on an unrounded exponent and an unrounded mantissa; as well as perform a rounding correction for the addend in parallel to the actual alignment shift, responsive to a rounding-up signal.

First claim

What is claimed is:

1. A method of performing binary floating point arithmetic calculations in a modified floating-point fused multiply-add unit configured to operate on an addend, a multiplier, and a multiplicand, the method comprising:
receiving as the addend an unrounded result of a prior operation executed in the unit via an early result feedback path;
performing an alignment shift by a shift amount, of the addend on an unrounded exponent and an unrounded mantissa;
in parallel to performing the alignment shift, performing a rounding correction for the addend by a correction term applied to a multiplier reduction tree of the unit, the rounding correction being enabled by a rounding-up signal; and
performing at least one of:
obtaining the correction term by applying a decode function to the shift amount, based on an effective addition; or
obtaining the correction term by applying a half-decode function to the shift amount, based on an effective subtraction.

2. The method according to claim 1 , wherein multiple floating-point precisions are supported, and wherein a value of the correction term is adapted to support unrounded forwarding for a result of one or more of the supported multiple floating-point precisions.

3. The method according to claim 1 , further comprising generating the correction term based on incrementing an unrounded intermediate result of the prior operation.

4. The method according to claim 1 , wherein the performing the alignment shift further comprises performing the alignment shift by a sum-addressed shifter.

5. The method according to claim 1 , wherein the prior operation is at least one of an addition, a multiplication, or a multiply-add operation.

6. The method according to claim 1 , wherein a sum or an absolute difference between the addend and a product of the multiplier and the multiplicand is calculated, the sum or the absolute difference including sticky bits.

7. The method according to claim 6 , further comprising calculating a correction term used by the performing the rounding correction based on the sticky bits of the sum or the absolute difference.

8. The method according to claim 1 , wherein the performing the alignment shift comprises calculating the shift amount and shifting an operand.

9. A method of performing binary floating point arithmetic calculations in a modified floating-point fused multiply-add unit configured to operate on an addend, a multiplier, and a multiplicand, the method comprising:
receiving as the addend an unrounded result of a prior operation executed in the unit via an early result feedback path;
performing an alignment shift by a shift amount, of the addend on an unrounded exponent and an unrounded mantissa, wherein performing the alignment shift comprises calculating the shift amount and shifting an operand;
in parallel to performing the alignment shift, performing a rounding correction for the addend, the rounding correction being enabled by a rounding-up signal; and
generating a correction term used by the performing the rounding correction based on the shift amount.

10. The method of claim 9 , wherein the performing the alignment shift further comprises performing the alignment shift by a sum-addressed shifter.

11. The method of claim 9 , wherein the prior operation is at least one of an addition, a multiplication, or a multiply-add operation.

12. The method of claim 9 , wherein a sum or an absolute difference between the addend and a product of the multiplier and the multiplicand is calculated, the sum or the absolute difference including sticky bits.

13. The method of claim 12 , wherein the method further comprises calculating a correction term used by the performing the rounding correction based on the sticky bits of the sum or the absolute difference.

14. The method of claim 9 , wherein the performing the rounding correction further comprises performing the rounding correction for the addend by a correction term applied to a multiplier reduction tree of the unit.

Assignees

• IBM

Inventors

• Klein Michael
• Kroener Klaus M
• Lichtenau Cédric
• Mueller Silvia Melitta

Classifications

• G06F7/483 Primary

  Computations with numbers represented by a non-linear combination of denominational numbers, e.g. rational numbers, logarithmic number system or floating-point numbers {(G06F7/4806, G06F7/4824, G06F7/49, G06F7/491, G06F7/544 take precedence)} · CPC title

• G06F5/01

  for shifting, e.g. justifying, scaling, normalising {(digital stores in which the information is moved stepwise, e.g. shift-registers G11C19/00; digital stores in which the information circulates G11C21/00)} · CPC title

• G06F7/5443

  Sum of products (for applications thereof, see the relevant places, e.g. G06F17/10, H03H17/00) · CPC title

• G06F5/012

  in floating-point computations · CPC title

• G06F7/4876 Primary

  Multiplying · CPC title