Compute-in-memory devices and methods for operating the same
US-2025217106-A1 · Jul 3, 2025 · US
Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even
Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even · Cooperative Patent Classification (CPC)
Computing, optics, measurement, and control technologies.
Related technology areas
Mapped technology topics for this CPC code.
| Metric | Value |
|---|---|
| CPC code | G06F7/533 |
| Official title | Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even |
| Display label | Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even |
| Total patents | 61 |
Filing trend
Year-over-year patent counts classified under this CPC code.
Filing activity over the last five years is rapidly growing.
| Year | Patents |
|---|---|
| 2015 | 4 |
| 2016 | 6 |
| 2017 | 4 |
| 2018 | 1 |
| 2019 | 3 |
| 2020 | 14 |
| 2021 | 2 |
| 2022 | 4 |
| 2023 | 9 |
| 2024 | 7 |
| 2025 | 7 |
Representative patents
Representative publications under this CPC code from precomputed stats, or recent filings when stats are unavailable.
Multiplication method and electronic circuit
US-2025110696-A1 · Apr 3, 2025 · US
Processing element, neural processing device including same, and multiplication operation method using same
US-12236209-B2 · Feb 25, 2025 · US
Multiplier and adder in systolic array
US-12197890-B2 · Jan 14, 2025 · US
Custom Scratchpad Memory For Partial Dot Product Reductions
US-2025013432-A1 · Jan 9, 2025 · US
Systems and methods for performing double precision high-speed arithmetic operation
US-2025004719-A1 · Jan 2, 2025 · US
Calculation circuit and deep learning system including the same
US-12141545-B2 · Nov 12, 2024 · US
Multiplication circuitry, apparatus, system, chip-containing product, method and computer-readable medium
US-2024329932-A1 · Oct 3, 2024 · US
Multiplier
US-2024168715-A1 · May 23, 2024 · US
Integer square 1ulp hardware multiplier
US-2024160407-A1 · May 16, 2024 · US
Processing element, neural processing device including same, and multiplication operation method using same
US-2024086150-A1 · Mar 14, 2024 · US
Information processing apparatus, information processing method, and information processing program
US-2024061646-A1 · Feb 22, 2024 · US
Processing element, neural processing device including same, and multiplication operation method using same
US-11868741-B2 · Jan 9, 2024 · US
Method and apparatus for efficient binary and ternary support in fused multiply-add (FMA) circuits
US-11836464-B2 · Dec 5, 2023 · US
Method and device with convolution neural network processing
US-11836971-B2 · Dec 5, 2023 · US
Method and apparatus with repeated multiplication
US-2023385025-A1 · Nov 30, 2023 · US
Counting elements in neural network input data
US-11734002-B2 · Aug 22, 2023 · US
Processing apparatus and processing method
US-11720353-B2 · Aug 8, 2023 · US
Processing apparatus and processing method
US-11698786-B2 · Jul 11, 2023 · US
Semiconductor device
US-2023162013-A1 · May 25, 2023 · US
Frequently asked questions
Answers are generated from the same data shown on this page.
- What is CPC G06F7/533?
- CPC G06F7/533 is the Cooperative Patent Classification code for “Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even.”
- How many patents are filed under CPC G06F7/533 (Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even)?
- Our database includes 61 publications tagged with this CPC code.
- Is patent activity under CPC G06F7/533 growing?
- Publication counts under this code: 7 in 2024 vs 7 in 2025 (latest complete years).