Method for lithography patterning

Patent metadata

Field	Value
Publication number	US-9274417-B2
Application number	US-201314030926-A
Country	US
Kind code	B2
Filing date	Sep 18, 2013
Priority date	Sep 18, 2013
Publication date	Mar 1, 2016
Grant date	Mar 1, 2016

Abstract

A method for lithography patterning is disclosed. An exemplary method includes receiving an IC design layout, the IC design layout having an IC pattern and receiving a mask, the mask having a defect. The method further includes making at least one mark on the mask in relation to the defect; positioning the IC design layout over the mask thereby covering the defect by the IC pattern; and patterning the mask with the IC design layout.

First claim

What is claimed is:

1. A method comprising:
receiving an IC design layout, wherein the IC design layout includes an IC pattern;
receiving a mask for receiving the IC design layout, wherein the mask includes a defect;
making at least one mark on the mask in relation to the defect by one of: forming a cavity into the mask directly over the defect, and depositing the at least one mark over a top surface of the mask at a first distance from the defect;
positioning the IC design layout over the mask thereby covering the defect by the IC pattern; and
after the positioning, patterning the mask with the IC design layout.

2. The method of claim 1 , wherein the defect has a dimension smaller than a threshold of the IC design layout.

3. The method of claim 1 , wherein the mask is an extreme ultraviolet (EUV) mask, and wherein the patterning of the mask includes:
forming a resist layer over an absorber layer of the mask;
modifying the resist layer using the IC design layout to include a plurality of openings; and
etching the absorber layer through the plurality of openings thereby forming the IC pattern in the absorber layer.

4. The method of claim 1 , wherein the making of the at least one mark is by the forming of the cavity, wherein:
the mask is an extreme ultraviolet (EUV) mask having an absorber layer;
the absorber layer has a first thickness; and
a depth of the cavity is substantially smaller than the first thickness.

5. The method of claim 1 , wherein the making of the at least one mark is by the depositing of the at least one mark, further comprising, before the patterning of the mask with the IC design layout:
removing the at least one mark.

6. The method of claim 5 , wherein:
the mask is an extreme ultraviolet (EUV) mask having an absorber layer and a protection layer over the absorber layer;
the protection layer includes tantalum boron oxide;
the at least one mark includes chromium; and
the removing the at least one mark includes a plasma etching process.

7. The method of claim 1 , wherein:
the mask is an extreme ultraviolet (EUV) mask; and
the defect is a phase defect.

8. The method of claim 1 , wherein the defect is one of: a bump defect and a pit defect.

9. The method of claim 1 , further comprising:
receiving a wafer, the wafer having a substrate and a resist layer over the substrate; and
exposing the resist layer to a radiation using the patterned mask.

10. The method of claim 9 , wherein:
the substrate includes silicon; and
the radiation is an EUV radiation.

11. A method comprising:
receiving an IC design layout and an EUV mask, wherein the IC design layout includes an IC pattern and the EUV mask includes a phase defect;
determining a size of the phase defect;
depositing at least one mark on the EUV mask in relation to the phase defect if and only if the size of the phase defect is smaller than a threshold;
positioning the IC design layout over the EUV mask, wherein the IC pattern covers the phase defect; and
patterning the EUV mask with the IC design layout thereby covering the phase defect underneath an absorber layer of the patterned EUV mask.

12. The method of claim 11 , further comprising:
receiving a wafer, the wafer having a silicon substrate and a resist layer over the silicon substrate; and
exposing the resist layer to an EUV radiation using the patterned EUV mask.

13. The method of claim 11 , further comprising:
etching the at least one mark before the patterning of the EUV mask with the IC design layout.

14. The method of claim 11 , wherein the determining the size of the phase defect includes:
using a defect map associated with the EUV mask, wherein the defect map identifies the phase defect.

15. A method comprising:
receiving an IC design layout, an EUV mask, and a defect map, wherein the defect map identifies a plurality of phase defects of the EUV mask;
selecting at least one of the phase defects, wherein a dimension of the selected phase defect is smaller than a threshold;
forming a cavity in an absorber layer of the EUV mask directly over the selected phase defect, wherein a depth of the cavity is less than a thickness of the absorber layer and a dimension of the cavity on a surface of the EUV mask is greater than the threshold;
positioning the IC design layout over the EUV mask thereby covering the plurality of phase defects with the IC design layout; and
patterning the EUV mask with the IC design layout.

16. The method of claim 11 , wherein the at least one mark includes two marks and the phase defect is located on a straight line between the two marks.

17. The method of claim 11 , wherein the at least one mark include chromium.

18. The method of claim 11 , wherein the at least one mark and the phase defect are simultaneously within a viewing area of an overlay metrology tool.

19. The method of claim 15 , wherein the forming of the cavity includes punching the surface of the EUV mask directly over the selected phase defect.

20. The method of claim 15 , further comprising:
depositing at least one mark on the EUV mask near another phase defect for locating the another phase defect.

Assignees

• Taiwan Semiconductor Mfg

Inventors

• Shih Hsun-Chuan
• Chu Yuan-Chih

Classifications

• G03F1/80 Primary

  Etching · CPC title

• G03F1/84

  Inspecting · CPC title

• G03F1/72 Primary

  Repair or correction of mask defects · CPC title

• G03F1/22 Primary

  Masks or mask blanks for imaging by radiation of 100nm or shorter wavelength, e.g. X-ray masks, extreme ultraviolet [EUV] masks; Preparation thereof · CPC title