Emitter-coupled spin-transistor logic

Patent metadata

Field	Value
Publication number	US-9270277-B2
Application number	US-201313931552-A
Country	US
Kind code	B2
Filing date	Jun 28, 2013
Priority date	Jun 28, 2012
Publication date	Feb 23, 2016
Grant date	Feb 23, 2016

Abstract

An emitter-coupled spin-transistor includes an emitter, a collector and a base. A first control wire receives an input current to create a magnetic field that affects amplification of the spin-transistor. A second transistor also includes an emitter, a collector and a base, where the emitter of the second transistor is coupled to the emitter of the spin-transistor to provide a logic circuit.

First claim

What is claimed is:

1. A logic circuit, comprising:
a spin-transistor having an emitter, a collector and a base;
a first control wire for receiving an input current to create a magnetic field that affects amplification of the spin-transistor;
a first resistor between the spin-transistor collector and one of a low voltage source and a high voltage source;
a second transistor having an emitter, a collector and a base, wherein the emitter of the second transistor is coupled to the emitter of the spin-transistor;
a second resistor between the second transistor collector and the one of the low voltage source and the high voltage source; and
a third resistor between the spin-transistor emitter and the other of the low voltage source and the high voltage source.

2. The logic circuit of claim 1 , wherein the second transistor comprises a second spin-transistor and a second control wire for receiving a second current to create a magnetic field that affects amplification of the second spin-transistor.

3. The logic circuit of claim 1 , further comprising:
a third transistor having an emitter, a collector and a base; and
a fourth resistor between the third transistor collector and the one of the low voltage source and the high voltage source, wherein the current through the fourth resistor feeds the first control wire.

4. The logic circuit of claim 3 , wherein the third transistor comprises a spin-transistor.

5. The logic circuit of claim 1 , further comprising a shield to concentrate the magnetic field through the spin-transistor.

6. The logic circuit of claim 1 , wherein the spin-transistor comprises any electrical device with amplification affected by applied magnetic field, such as a pnp bipolar junction transistor, npn bipolar junction transistor, n-type metal-oxide-semiconductor field-effect transistor (MOSFET), or p-type MOSFET.

7. The logic circuit of claim 1 , wherein the spin-transistor has either a positive magnetoresistance or a negative magnetoresistance, and is either ferromagnetic/non-volatile or paramagnetic/volatile.

8. The logic circuit of claim 1 , further comprising a voltage follower connected to an output of the logic circuit.

9. An inverter/buffer comprising the logic circuit of claim 1 .

10. A full adder comprising the logic circuit of claim 1 .

11. A 2:1 multiplexer comprising the logic circuit of claim 1 .

12. A 4:1 multiplexer comprising the logic circuit of claim 1 .

13. The logic circuit of claim 1 , where the first control wire comprises multiple control wires.

14. A logic circuit, comprising:
a first spin-transistor having an emitter, a collector and a base;
a first control wire for receiving an input current to create a magnetic field that affects amplification of the first spin-transistor;
a first resistor between the first spin-transistor collector and one of a low voltage source and a high voltage source;
a second spin-transistor having an emitter, a collector and a base, wherein the emitter of the second spin-transistor is coupled to the emitter of the first spin-transistor;
a second control wire for receiving an input current to create a magnetic field that affects amplification of the second spin-transistor;
a second resistor between the second spin-transistor collector and the one of the low voltage source and the high voltage source;
a third resistor between the first spin-transistor emitter and the other of the low voltage source and the high voltage source; and
a third transistor having an emitter, a collector and a base; and
a fourth resistor between the third transistor collector and the one of the low voltage source and the high voltage source, wherein the current through the fourth resistor feeds the second control wire for the second spin-transistor.

15. The logic circuit of claim 14 , where one or both of the first control wire and the second control wire comprises multiple control wires.

16. The logic circuit of claim 14 , further comprising multiple input circuits connected with the first spin-transistor, comprising:
an additional spin-transistor having an emitter, a collector and a base, wherein the emitter of the additional spin-transistor is coupled to the emitter of the first spin-transistor;
an additional control wire for receiving an input current to create a magnetic field that affects amplification of the additional spin-transistor; and
an additional resistor between the additional spin-transistor collector and the one of the low voltage source and the high voltage source.

17. A full adder comprising the logic circuit of claim 14 .

18. A 2:1 multiplexer comprising the logic circuit of claim 14 .

19. A 4:1 multiplexer comprising the logic circuit of claim 14 .

20. The logic circuit of claim 14 , further comprising a shield to concentrate the magnetic field through the first spin-transistor.

Assignees

• Univ Northwestern

Inventors

• Friedman Joseph S
• Memik Gokhan
• Wessels Bruce W

Classifications

• H03K19/086

  Emitter coupled logic · CPC title

• H03K19/082 Primary

  using bipolar transistors · CPC title

• H03K19/094 Primary

  using field-effect transistors · CPC title

• H10D48/385

  Devices using spin-polarised carriers · CPC title

• H10D48/40 Primary

  Devices controlled by magnetic fields · CPC title