Current steering level-shifter

Patent metadata

Field	Value
Publication number	US-11489526-B2
Application number	US-202016882407-A
Country	US
Kind code	B2
Filing date	May 22, 2020
Priority date	Dec 21, 2018
Publication date	Nov 1, 2022
Grant date	Nov 1, 2022

Abstract

Described is a level-shifter that can save area between voltage domains with limited voltage differential, and further save power by steering current between two power supply rails. The level-shifter comprises: an input to receive a first signal between a first reference rail and a second reference rail; an output to provide a second signal the first reference rail and a third reference rail, wherein in a voltage level of the third reference rail is higher than a voltage level of the second reference rail, and wherein a voltage level of the first reference is lower than the voltage level of the second reference rail and the third reference rail; and a circuitry coupled to the input and the output, wherein the circuitry is to steer current from the third reference rail to the second reference rail.

First claim

We claim:

1. An apparatus comprising:
a first inverter to receive an input which has a voltage swing between a first power supply voltage and ground;
a second inverter to receive a first output of the first inverter, wherein the second inverter is to generate a second output which has a voltage swing between a second power supply voltage and the ground; and
a first transistor coupled to the first inverter and a first power supply rail, wherein the first power supply rail provides the first power supply voltage, wherein the first transistor is controllable by the second output; and
a second transistor coupled to the first transistor and the ground, wherein the second transistor comprises an n-type transistor having a gate terminal coupled to the ground.

2. The apparatus of claim 1 , wherein the first inverter comprises at least three transistors coupled in series between the ground and a second power supply rail, wherein the second power supply rail is to provide the second power supply voltage.

3. The apparatus of claim 2 , wherein the at least three transistors of first inverter include:
an n-type transistor having a gate terminal to receive the input, wherein the n-type transistor is coupled to the ground and the first output; and
a first p-type transistor coupled is series with the n-type transistor, wherein the first p-type transistor has a gate terminal to receive the input, wherein the first p-type transistor is coupled to the first output.

4. The apparatus of claim 3 , wherein the at least three transistors of the first inverter further include:
a second p-type transistor coupled is series with the first p-type transistor, wherein the second p-type transistor has a gate terminal to receive the input, wherein the second p-type transistor is coupled to the second power supply rail.

5. The apparatus of claim 4 , wherein a source terminal of the first transistor is connected to the first p-type transistor and the second p-type transistor, and wherein a drain terminal of the first transistor is connected to the first power supply rail.

6. The apparatus of claim 1 , wherein the first transistor comprises an n-type transistor.

7. The apparatus of claim 1 , further comprising a third transistor coupled to the second output and the ground, wherein the third transistor has a gate terminal controllable by an enable.

8. An apparatus comprising:
a first inverter to receive an input which has a voltage swing between a first power supply voltage and ground, wherein the first inverter includes at least three transistors coupled in series between the ground and a second power supply rail;
a second inverter to receive a first output of the first inverter, wherein the second inverter is to generate a second output which has a voltage swing between a second power supply voltage and the ground; and
a circuitry coupled to the first output and the second output, wherein the circuitry is to steer current from the second power supply rail, that provides the second power supply voltage, to a first power supply rail, that provides the first power supply voltage, wherein the circuitry comprises:
a first transistor coupled to the first inverter and the first power supply rail, wherein the transistor is controllable by the second output; and
a second transistor coupled to the first transistor and the ground, wherein the second transistor comprises an n-type transistor having a gate terminal coupled to the ground.

9. The apparatus of claim 8 , wherein the first transistor comprises an n-type transistor.

10. A system comprising:
a memory;
a processor coupled to the memory; and
a wireless interface to allow the processor to communicate with another device, wherein the processor comprises a level-shifter which includes:
a first inverter to receive an input which has a voltage swing between a first power supply voltage and ground;
a second inverter to receive a first output of the first inverter, wherein the second inverter is to generate a second output which has a voltage swing between a second power supply voltage and ground; and
a circuitry coupled to the first output and the second output, wherein the circuitry is to steer current from a second power supply rail, that provides the second power supply voltage, to a first power supply rail, that provides the first power supply voltage, wherein the circuitry includes a first transistor coupled to the first inverter and the first power supply rail, wherein the first transistor is controllable by the second output; and
a second transistor coupled to the first transistor and the ground, wherein the second transistor comprises an n-type transistor having a gate terminal coupled to the ground.

11. The system of claim 10 , wherein the first inverter comprises at least three transistors coupled in series between ground and the second power supply rail.

12. The system of claim 10 , wherein the first transistor comprises an n-type transistor.

13. An apparatus comprising:
a first inverter to receive an input which has a voltage swing between a first power supply voltage and ground;
a second inverter to receive a first output of the first inverter, wherein the second inverter is to generate a second output which has a voltage swing between a second power supply voltage and the ground; and
a first transistor coupled to the first inverter and a first power supply rail, wherein the first power supply rail provides the first power supply voltage, wherein the first transistor is controllable by the second output;
a second transistor coupled to the first transistor and the ground; and
a third transistor coupled to the second output and the ground, wherein the third transistor has a gate terminal controllable by an enable signal.

14. The apparatus of claim 13 , wherein the second transistor is an n-type transistor with a gate terminal coupled to the ground.

15. The apparatus of claim 13 , wherein the first transistor is an n-type transistor.

16. The apparatus of claim 13 , wherein the first inverter comprises at least three transistors coupled in series between the ground and a second power supply rail, wherein the second power supply rail is to provide the second power supply voltage.

Assignees

• Intel Corp

Inventors

• Mora Andres Malavasi
• Kulkarni Jaydeep
• Thaploo Anupama
• Khellah Muhammad

Classifications

• H03K19/082 Primary

  using bipolar transistors · CPC title

• H03K19/017509 Primary

  Interface arrangements · CPC title

• H03K19/0948

  using CMOS {or complementary insulated gate field-effect transistors} · CPC title