Monitor test key of epi profile

Patent metadata

Field	Value
Publication number	US-9269641-B2
Application number	US-201414555314-A
Country	US
Kind code	B2
Filing date	Nov 26, 2014
Priority date	Dec 23, 2011
Publication date	Feb 23, 2016
Grant date	Feb 23, 2016

Abstract

A method and apparatus for estimating a height of an epitaxially grown semiconductor material in other semiconductor devices. The method includes epitaxially growing first, second, and third portions of semiconductor material on a first semiconductor device, measuring a height of the third portion of semiconductor material and a height of the first or second portion of semiconductor material, measuring a first saturation current through the first and second portions of semiconductor material, measuring a second saturation current through the first and third portions of semiconductor material, and preparing a model of the first saturation current relative to the height of the first or second portion of semiconductor material and the second saturation current relative to an average of the height of the first and third portions of semiconductor material. The model is used to estimate the height of an epitaxially grown semiconductor material in the other semiconductor devices.

First claim

What is claimed is:

1. A method of estimating a height of an epitaxially grown semiconductor material, the method comprising:
epitaxially growing first, second, and third portions of semiconductor material on a first substrate;
measuring a first current through the first and second portions of semiconductor material;
measuring a second current through the first and third portions of semiconductor material;
preparing a model of the first current relative to an average height of the first and second portions of semiconductor material and the second current relative to an average of the height of the first and third portions of semiconductor material; and
using the model to estimate the height of an epitaxially grown semiconductor material in other semiconductor devices.

2. The method of claim 1 , wherein the third portion of semiconductor material is epitaxially grown adjacent to an environment that inhibits epitaxial growth.

3. The method of claim 1 , wherein the third portion of semiconductor material is epitaxially grown adjacent to at least one of silicon nitride and an oxide.

4. The method of claim 1 , further comprising:
epitaxially growing fourth and fifth portions of semiconductor material, the fourth and fifth portions of semiconductor material having a similar height as the third portion of semiconductor material;
measuring a third current through the fourth and fifth portions of semiconductor material; and
preparing the model to include the third current relative to the height the fourth and fifth portions of semiconductor material.

5. The method of claim 1 , further comprising:
forming a first fin, the first fin being interposed between the first portion and the second portion; and
forming a first gate electrode over the first fin.

6. The method of claim 5 , further comprising:
forming a second fin, the second fin being interposed between the second portion and the third portion; and
forming a second gate electrode over the second fin.

7. The method of claim 1 , further comprising forming contacts to each of the first, second, and third portions of semiconductor material.

8. The method of claim 1 , further comprising forming a first set of spaced apart contacts on the first portion of semiconductor material, a second set of spaced apart contacts on the second portion of semiconductor material, and a third set of spaced apart contacts on the third portion of semiconductor material to permit measurement of the first and second currents.

9. A system for estimating a height of an epitaxially grown semiconductor material in semiconductor devices, the system comprising:
a first semiconductor device having a first average height of epitaxially grown semiconductor material;
a second semiconductor device having a second average height of epitaxially grown semiconductor material;
contacts electrically coupled to the first semiconductor device and the second semiconductor device; and
a model illustrating a first saturation current passing through the contacts electrically coupled to the first semiconductor device and a second saturation current passing through the contacts electrically coupled to the second semiconductor device.

10. The system of claim 9 , wherein the first semiconductor device comprises a first portion and a second portion of epitaxially grown semiconductor material, the first portion and second portion having a first height, and wherein the second semiconductor device comprises a third portion and a fourth portion, the third portion having the first height and the fourth portion having a second height.

11. The system of claim 10 , wherein the third portion and the second portion are a same portion.

12. The system of claim 10 , wherein the first portion and the second portion of epitaxially grown semiconductor material are separated by a gate electrode.

13. The system of claim 12 , wherein the second portion and third portion of epitaxially grown semiconductor material are separated by a second gate electrode.

14. The system of claim 9 , further comprising:
a third semiconductor device having a third average height of epitaxially grown semiconductor material;
wherein the model illustrates a third saturation current passing through contacts to the third semiconductor device.

15. The system of claim 14 , wherein the third semiconductor device comprises a fifth portion and a sixth portion of epitaxially grown semiconductor material, the fifth portion and sixth portion having the second height.

16. A method of estimating a height of an epitaxially grown semiconductor layer, the method comprising:
measuring a saturation current through a first epitaxial region; and
estimating a height of the first epitaxial region based on a predetermined relationship between the saturation current and the height.

17. The method of claim 16 , wherein the predetermined relationship between the saturation current and the height comprises:
measuring a first current through a first semiconductor device, the first semiconductor device having a first and second epitaxial portions, the first and second epitaxial portions having a first average height;
measuring a second current through a second semiconductor device, the second semiconductor device having a third and fourth epitaxial portions, the third and fourth epitaxial portions having a second average height, the first average height being different than the second average height; and
determining the predetermined relationship based upon the first current, the second current, the first average height, and the second average height.

18. The method of claim 17 , wherein the first epitaxial portion, the second epitaxial portion, and the third epitaxial portion have a first height, and the fourth epitaxial portion has a second height different than the first height.

19. The method of claim 17 , wherein the first epitaxial portion and the second epitaxial portion have a first height, and the third epitaxial portion and the fourth epitaxial portion has a second height different than the first height.

20. The method of claim 17 , wherein the predetermined relationship between the saturation current and the height further comprises:
measuring a third current through a third semiconductor device, the third semiconductor device having a fifth and sixth epitaxial portions, the fifth and sixth epitaxial portions having a third average height;
wherein the determining the predetermined relationship comprises determining the predetermined relationship based upon the third current and the third average height.

Assignees

• Taiwan Semiconductor Mfg

Inventors

• Chang Chih-Sheng
• Ho Chia-Cheng
• Lin Yi-Tang

Classifications

• H10P74/277

  Circuits for electrically characterising or monitoring manufacturing processes, e.g. circuits in tested chips or circuits in testing wafers · CPC title

• H10P74/203 Primary

  Structural properties, e.g. testing or measuring thicknesses, line widths, warpage, bond strengths or physical defects · CPC title

• H10P74/00 Primary

  Testing or measuring during manufacture or treatment of wafers, substrates or devices · CPC title

• H10D84/0158 Primary

  the components including FinFETs · CPC title

• H10D84/038

  using silicon technology, e.g. SiGe · CPC title