SOI wafer, manufacturing method therefor, and MEMS device

Patent metadata

Field	Value
Publication number	US-9266715-B2
Application number	US-201414193209-A
Country	US
Kind code	B2
Filing date	Feb 28, 2014
Priority date	Apr 24, 2012
Publication date	Feb 23, 2016
Grant date	Feb 23, 2016

Abstract

In order to obtain a SOI wafer having an excellent ability of gettering metal impurities, an efficient method of manufacturing a SOI wafer, and a highly reliable MEMS device using such a SOI wafer, provided is a SOI wafer including: a support wafer ( 1 ) and an active layer wafer ( 6 ) which are bonded together with an oxide film ( 3 ) therebetween, each of the support wafer ( 1 ) and the active layer wafer ( 6 ) being a silicon wafer; a cavity ( 1 b ) formed in a bonding surface of at least one of the silicon wafers; and a gettering material ( 2 ) formed on a surface on a side opposite to the bonding surface.

First claim

What is claimed is:

1. A silicon on insulator (SOI) wafer, comprising:
a first silicon wafer and a second silicon wafer which are bonded together with an oxide film therebetween;
a cavity formed on a bonding surface of the first silicon wafer; and
a gettering material that is formed on a surface of the first silicon wafer on a side opposite to the bonding surface.

2. The SOI wafer according to claim 1 , wherein the gettering material comprises a crushed layer.

3. The SOI wafer according to claim 1 , wherein the gettering material comprises a polysilicon thin film.

4. A MEMS device comprising:
the SOI wafer according to claim 1 ;
a diaphragm formed by grinding a silicon wafer on the side opposed to the cavity; and
a distortion detecting unit formed on the diaphragm.

5. The MEMS device according to claim 4 , wherein the distortion detecting unit comprises a piezoelectric resistance.

6. The SOI wafer according to claim 1 , wherein metal impurities attached to the bonding surface move toward the gettering material through the first silicon wafer.

7. A silicon on insulator (SOI) wafer, comprising:
a first silicon wafer and a second silicon wafer which are bonded together with an oxide film therebetween;
a cavity formed on a bonding surface of the first silicon wafer; and
a gettering material that is formed on a surface of the second silicon wafer on a side opposite to the bonding surface of the first silicon wafer and absorbs metal impurities attached to the bonding surface.

8. The SOI wafer according to claim 7 , wherein the metal impurities move toward the gettering material through the second silicon wafer.

Assignees

• Yoshikawa Eiji
• Ichikawa Jyunichi
• Yoshida Yukihisa
• Mitsubishi Electric Corp

Inventors

• Yoshikawa Eiji
• Ichikawa Jyunichi
• Yoshida Yukihisa

Classifications

• H10W10/181

  Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers · CPC title

• H10P90/1924

  with separation/delamination along a porous layer · CPC title

• H10W76/48

  Fillings including materials for absorbing or reacting with moisture or other undesired substances · CPC title

• H10D62/83

  being Group IV materials, e.g. B-doped Si or undoped Ge · CPC title

• B81B7/0038 Primary

  using materials for controlling the level of pressure, contaminants or moisture inside of the package, e.g. getters · CPC title