System and method for providing voltage supply protection in a memory device

Patent metadata

Field	Value
Publication number	US-9251864-B2
Application number	US-201213605129-A
Country	US
Kind code	B2
Filing date	Sep 6, 2012
Priority date	Sep 6, 2012
Publication date	Feb 2, 2016
Grant date	Feb 2, 2016

Abstract

The invention relates to an electronic memory system, and more specifically, to a system for providing voltage supply protection in a memory device, and a method for providing voltage supply protection in a memory device. According to an embodiment, a system for providing voltage supply protection in a memory device is provided, the system including a memory array including a plurality of memory cells arranged in a plurality of groups of memory cells, and a plurality of current limiting elements, wherein each group of memory cells is associated with at least one current limiting element.

First claim

What is claimed is:

1. A system for providing voltage supply protection in a memory device comprising:
a memory array comprising a plurality of memory cells arranged in a plurality of groups of memory cells;
a control logic;
at least one monitoring device, wherein the at least one monitoring device is configured to monitor a parameter indicative of a defect in the memory array; and
at least one current limiting element,
wherein at least one group of memory cells of the plurality of groups of memory cells is associated with the at least one current limiting element,
wherein the current limiting element comprises a switching element; and
wherein the control logic is configured to receive signals from the at least one monitoring device and control the at least one current limiting element in response thereto.

2. The system of claim 1 , wherein the memory device comprises a non-volatile memory device, the memory array comprises a non-volatile memory array, and the memory cells comprise non-volatile memory cells.

3. The system of claim 1 , further comprising:
a first voltage supply source, wherein the at least one group of memory cells of the plurality of groups of memory cells is connected to the first voltage supply source by a respective voltage supply line.

4. The system of claim 3 , wherein the voltage supply line comprises the at least one current limiting element.

5. The system of claim 4 , further comprising:
a second voltage supply source connected to the at least one group of memory cells of the plurality of groups of memory cells.

6. The system of claim 5 , wherein the first voltage supply source comprises a first charge pump and the second voltage supply source comprises a second charge pump, and wherein the current limiting element is configured to ensure that the first and second charge pumps do not drive against each other in the presence of a defect in the memory array.

7. The system of claim 5 , wherein the current limiting element is configured to isolate the first voltage supply source from the second voltage supply source in the presence of a defect in the memory array.

8. The system of claim 1 , wherein the switching element is a transistor.

9. The system of claim 1 , wherein the monitoring device is configured to monitor the parameter associated with the at least one group of memory cells.

10. The system of claim 9 , wherein the parameter comprises a current or voltage or an impedance.

11. A system for providing voltage supply protection in a non-volatile memory device comprising:
a non-volatile memory array comprising a plurality of non-volatile memory cells arranged in a plurality of groups of non-volatile memory cells;
at least one current limiting element;
at least one monitoring device, wherein the at least one monitoring device is configured to monitor a parameter indicative of a defect in the non-volatile memory array; and
a control logic configured to receive signals from the at least one monitoring device and control the at least one current limiting element in response thereto,
wherein the at least one current limiting element and the at least one monitoring device is associated with a respective group of non-volatile memory cells of the plurality of groups of non-volatile memory cells.

12. The system of claim 11 , wherein the monitoring device is configured to monitor the parameter indicative of a defect in the group of non-volatile memory cells associated with the monitoring device.

13. The system of claim 12 , wherein current limiting element is configured to limit a current if evaluation of the parameter by the monitoring device indicates a defect in the respective group of non-volatile memory cells of the plurality of groups of non-volatile memory cells.

14. A system for providing voltage supply protection in a non-volatile memory device comprising:
means for storing data in a non-volatile manner;
means for providing a first voltage;
means for connecting the means for storing data in a non-volatile manner to the means for providing a first voltage;
means for detecting a fault condition in the means for storing data in a non-volatile manner;
means for limiting a current in the means for storing data in a non-volatile manner; and
means for receiving signals from means for detecting a fault condition in the means for storing data in a non-volatile manner and controlling the means for limiting a current in the means for storing data in a non-volatile manner in response thereto,
wherein the means for limiting a current is integrated into the means for connecting the means for storing data in a non-volatile manner to the means for providing a first voltage.

15. The system of claim 14 , furthermore comprising:
means for providing a second voltage; and
means for connecting the means for storing data in a non-volatile manner to the means for providing a second voltage,
wherein the means for limiting a current is adapted to isolate the first voltage from the second voltage in the event of a detected fault condition.

16. A method of providing voltage supply protection in a memory device comprising a memory array, the method comprising:
supplying the memory array with a first voltage;
monitoring a parameter indicative of a defect in the memory array;
evaluating the parameter indicative of a defect in the memory array by a control logic;
selectively limiting a current flowing in the memory array based on the evaluation if the evaluation indicates a defect in the memory array.

17. The method of claim 16 , wherein the memory device comprises a non-volatile memory device and the memory array comprises a non-volatile memory array.

18. The method of claim 16 , wherein the current flows through a defect in the memory array.

19. The method of claim 18 , wherein the first voltage is supplied to word-lines of the memory array.

20. The method of claim 18 , further comprising supplying the memory array with a second voltage.

21. The method of claim 20 , wherein the first voltage is supplied by a first voltage supply source comprising a first charge pump and the second voltage is supplied by a second voltage supply source comprising a second charge pump, and wherein the current flowing in the memory array is limited in a manner to ensure that the first and second charge pumps do not drive against each other in the presence of a fault condition in the memory array.

22. A method of operating a non-volatile memory device, the non-volatile memory device comprising a non-volatile memory array comprising a plurality of non-volatile memory cells arranged in a plurality of groups of non-volatile memory cells,
wherein at least one current limiting element and at least one monitoring device is associated with at least one group of non-volatile memory cells of the plurality of groups of non-volatile memory cells, the method comprising:
supplying the non-volatile memory array with a first voltage;
monitoring with the at least one monitoring device a parameter indicative of a defect in the group of non-volatile memory cells associated with the monitoring device; and
evaluating by a control logic, the parameter indicative of a defect in the group of non-volatile memory cells.

23. The method of claim 22 , further comprising:
evaluating the parameter; and
if evaluation of the parameter indicates a defect in the group of non-volatile memory cells, limiting a current with the at least one current limiting element associate

Assignees

• Otterstedt Jan
• Allers Wolf
• Jefremow Mihail
• Paparisto Edvin
• Castro Leonardo
• Kern Thomas
• Infineon Technologies Ag

Inventors

• Otterstedt Jan
• Allers Wolf
• Jefremow Mihail
• Paparisto Edvin
• Castro Leonardo
• Kern Thomas

Classifications

• G11C29/832

  with disconnection of faulty elements · CPC title

• G11C29/02

  Detection or location of defective auxiliary circuits, e.g. defective refresh counters · CPC title

• G11C29/83 Primary

  with reduced power consumption · CPC title

• G11C29/04

  Detection or location of defective memory elements {, e.g. cell constructio details, timing of test signals} · CPC title

• G11C5/143 Primary

  Detection of memory cassette insertion or removal; Continuity checks of supply or ground lines; Detection of supply variations, interruptions or levels (G11C5/148 takes precedence); Switching between alternative supplies (G11C5/141 takes precedence) · CPC title