Semiconductor memory device and memory system including the same

Patent metadata

Field	Value
Publication number	US-9852815-B2
Application number	US-201615296428-A
Country	US
Kind code	B2
Filing date	Oct 18, 2016
Priority date	Jan 8, 2016
Publication date	Dec 26, 2017
Grant date	Dec 26, 2017

Abstract

A semiconductor memory device includes a normal memory block including a plurality of normal memory cells, a redundant memory block including a plurality of redundant memory cells used to replace defective cells among the normal memory cells, a normal buffer block configured to sense and amplify data stored in the normal memory block, a redundant buffer block configured to sense and amplify data stored in the redundant memory block, a normal latch block configured to fetch data from the normal buffer block and store the data based on a normal control signal, and a redundant latch block configured to selectively fetch data from the redundant buffer block and store the data based on a redundant control signal.

First claim

What is claimed is:

1. A semiconductor memory device comprising:
a normal memory block including a plurality of normal memory cells;
a redundant memory block including a plurality of redundant memory cells, the plurality of redundant memory cells configured to replace defective cells among the normal memory cells;
a normal buffer block configured to sense and amplify normal data stored in the normal memory block;
a redundant buffer block configured to sense and amplify redundant data stored in the redundant memory block, the redundant buffer block including a plurality of redundant buffers;
a normal latch block configured to fetch the normal data from the normal buffer block and store the normal data based on a normal control signal; and
a redundant latch block including a plurality of redundant latches each configured to selectively fetch the redundant data from a respective one of the plurality of redundant buffers and store the redundant data based on whether a redundant control signal designates that respective ones of the plurality of redundant latches are active redundant latches, the active redundant latches being ones of the plurality of redundant latches corresponding to bit lines connected to repair cells.

2. The semiconductor memory device of claim 1 , further comprising:
a control circuit configured to generate the normal control signal and the redundant control signal; and
a one-time programmable (OTP) memory configured to store a repair signal.

3. The semiconductor memory device of claim 2 , wherein the control circuit comprises:
a control signal generating circuit configured to generate the normal control signal to the normal latch block; and
a logic gate configured to generate the redundant control signal by performing a logic operation on the normal control signal and the repair signal.

4. The semiconductor memory device of claim 3 , wherein
the OTP memory is configured to store the repair signal based on a test of the semiconductor memory device, the repair signal indicating the active redundant latches.

5. The semiconductor memory device of claim 4 , wherein
the normal buffer block includes a plurality of normal buffers,
the normal latch block includes a plurality of normal latches, each of the normal latches configured to store data from a corresponding one of the normal buffers based on the normal control signal.

6. The semiconductor memory device of claim 3 , further comprising:
a circuit configured to output a control signal based on a defective address and a column address; and
a multiplexer configured to select one of the normal latch block and the redundant latch block based on the control signal.

7. The semiconductor memory device of claim 6 , wherein the defective address is a signal stored in the OTP memory, the signal indicating the column address of one of the defective cells.

8. The semiconductor memory device of claim 3 , wherein the logic gate comprises:
an AND gate configured to perform an AND operation on the normal control signal and the repair signal.

9. The semiconductor memory device of claim 1 , wherein
the plurality of redundant latches includes the active redundant latches and inactive redundant latches,
the redundant control signal designates the active redundant latches, and
the inactive redundant latches are configured not to receive and store data from corresponding redundant buffers.

10. A memory system comprising:
a plurality of semiconductor memory devices; and
a memory controller configured to control the semiconductor memory devices, wherein each of the semiconductor memory devices includes,
a memory cell array including a plurality of normal memory cells and a plurality of redundant memory cells, each of the plurality of redundant memory cells configured to replace a defective cell among the normal memory cells,
a sense amplifier configured to sense and amplify data stored in the memory cell array, the sense amplifier including a plurality of redundant buffers configured to sense and amplify data stored in the redundant memory cells,
a latch block configured to fetch and store data from the sense amplifier based on a normal control signal and a redundant control signal, the latch block including a plurality of redundant latches configured to selectively fetch redundant data from a respective one of the plurality of redundant buffers and store the redundant data based on whether the redundant control signal designates that respective ones of the plurality of redundant latches are active redundant latches, the active redundant latches being one of the plurality of redundant latches corresponding to bit lines connected to repair cells,
a control circuit configured to generate the normal control signal and the redundant control signal, and
a one time programmable (OTP) memory configured to store a repair signal.

11. The memory system of claim 10 , wherein
the active redundant latches are configured to operate based on the redundant control signal, and
the active redundant latches are configured to selectively fetch and store data from a corresponding one of the plurality of redundant buffers.

12. The memory system of claim 11 , wherein the control circuit comprises:
a control signal generating circuit configured to generate the normal control signal; and
a logic gate configured to generate the redundant control signal by performing a logic operation on the normal control signal and the repair signal.

13. The memory system of claim 12 , wherein
the OTP memory is configured to store the repair signal based on a test of the semiconductor memory device, the repair signal indicating a redundant latch assigned to a bit line connected to a repair cell among the plurality of redundant latches.

14. The memory system of claim 12 , wherein the OTP memory is one of a fuse, an anti-fuse, and a laser fuse.

15. A semiconductor memory device, comprising:
a latch block including a plurality of normal latches and a plurality of redundant latches, the plurality of redundant latches configured to selectively fetch redundant data from repair cells included in redundant memory cells based on a redundant control signal; and
a controller configured to selectively provide the redundant control signal to ones of the plurality of redundant latches based on a repair signal, the repair signal indicating which of the plurality of redundant latches are connected to the repair cells such that the controller is configured to selectively disable ones of the plurality of redundant latches not associated with the repair cells.

16. The semiconductor memory device of claim 15 , wherein
the plurality of normal latches are configured to fetch normal data from normal memory cells based on a normal control signal,
the repair cells are configured to replace defective cells among the normal memory cells, and
the controller is configured to selectively provide the redundant control signal to ones of the plurality of redundant latches, if the repair signal matches the normal control signal.

17. The semiconductor memory device of claim 16 , wherein the controller is configured to generate a control signal based on a defective address associated with the repair cells and a read address received from a decoder, and the semiconductor memory device further comprises:
a multiplexer configured to read one of the normal data from the plurality of normal latches and the redundant data from the plurality of redundant latches based on the control signal.

18. The semiconductor memory device of claim 15 , fu

Assignees

• Samsung Electronics Co Ltd

Inventors

• Lee Ho-Jun

Classifications

• G11C17/16

  using electrically-fusible links · CPC title

• G11C7/1012

  Data reordering during input/output, e.g. crossbars, layers of multiplexers, shifting or rotating · CPC title

• G11C7/06

  Sense amplifiers; Associated circuits {, e.g. timing or triggering circuits} · CPC title

• G11C29/78 Primary

  using programmable devices · CPC title

• G11C29/83

  with reduced power consumption · CPC title