Addressing auto address assignment and auto-routing in NAND memory network

Patent metadata

Field	Value
Publication number	US-9703702-B2
Application number	US-201314139164-A
Country	US
Kind code	B2
Filing date	Dec 23, 2013
Priority date	Dec 23, 2013
Publication date	Jul 11, 2017
Grant date	Jul 11, 2017

Abstract

A topology for memory circuits of a non-volatile memory system reduces capacitive loading. For a given channel, a single memory chip can be connected to the controller, but is in turn connected to multiple other memory devices that fan out in a tree-like structure, which can also fan back in to a single memory device. In addition to the usual circuitry, such as a memory arrays and associated peripheral circuitry, the memory chip also includes a flip-flop circuit and can function in several modes, including pass-through and active modes. Techniques are presented for the addressing of memory chips within such a topology, including an address assignment scheme.

First claim

It is claimed:

1. A non-volatile memory system comprising:
a memory section including:
a plurality of non-volatile memory circuits each having a first set of bus connections and a second set of bus connections; and
a bus structure connecting the plurality of non-volatile memory circuits in a tree-type arrangement that includes a front section and a back section,
wherein the front section comprises a series of multiple tiers in which each subsequent tier in the series has a higher number of memory circuits than a preceding tier with a last tier having the highest number of memory circuits,
wherein, for each tier except the last tier in the series, the second set of bus connections of memory circuits in each tier in the series branches out and connects to the first set of bus connections of one or more memory circuits of a subsequent tier in the series,
wherein the first set of bus connections of the one or more memory circuits in a first tier in the series connects to an input bus section,
wherein the back section comprises at least one tier with the same number of memory circuits as the tier preceding the last tier in the series from the front section; and
wherein the second set of bus connections of one or more memory circuits of the last tier of the back section connects to an output bus section; and

a controller circuit connected to the input bus section and to the output bus section, wherein the controller circuit is configured to determine a tier address for each of the memory circuits by propagating a signal from the input bus section through all the series of tiers according to a first clock, wherein the tier address is determined based on a number of cycles of the first clock required for the signal to propagate to a corresponding memory circuit.

2. The non-volatile memory system of claim 1 , wherein at least one of the memory circuits in one or more tiers in the series preceding the tier of an addressed memory circuit and that are in a path of the bus structure between the input bus section and the addressed memory circuit pass commands and data from the controller circuit to the tier of the addressed memory circuit.

3. The non-volatile memory system of claim 1 , wherein at least one of the memory circuits in one or more tiers in the series preceding the tier of an addressed memory circuit and that are in the path of the bus structure between the input bus section and the addressed memory circuit pass commands and data based on the tier address.

4. The non-volatile memory system of claim 1 , wherein at least one of the memory circuits in one or more tiers in the series preceding the tier of an addressed memory circuit and that are in the path of the bus structure between the input bus section and the addressed memory circuit pass commands and data according to a clock signal.

5. The non-volatile memory system of claim 1 , wherein the number of memory circuits in the first tier in the series from the front section is one.

6. The non-volatile memory system of claim 1 , wherein at least one of the memory circuits in each tier, except the last tier, in the series from the front section branches out into the same number of memory circuits as the memory circuits in a subsequent tier in the series.

7. The non-volatile memory system of claim 1 , wherein the second set of bus connections of one or more memory circuits in the at least one tier from the back section is connected to an output bus section, and wherein the output bus section connects to the controller circuit.

8. The non-volatile memory system of claim 1 , wherein the tree-type arrangement is symmetric with respect to the front section and the back section and has a common branching ratio.

9. The non-volatile memory system of claim 1 , wherein the controller circuit addresses the memory circuits via the input bus section and receives data from the memory circuits via the output bus section.

10. The non-volatile memory system of claim 1 , wherein, in response to addressing a memory circuit in the series, the controller circuit sets one or more of the memory circuits in one or more tiers in the series preceding the tier of the addressed memory circuit in a pass-through mode of operation or a sleep mode of operation.

11. The non-volatile memory system of claim 1 , wherein the controller circuit is configured to determine an intra-tier sub-address for each of the memory circuits by sequentially propagating a signal within each set of memory circuits branching out from a common memory circuit in the preceding tier according to a second clock, wherein the intra-tier address is determined based upon a number of cycles of the second clock required for the signal to propagate to a corresponding memory circuit.

12. A method of operating a non-volatile memory system, comprising:
assigning addresses to a plurality of memory circuits of the non-volatile memory system, wherein the memory circuits each have a first set of bus connections and a second set of bus connections and are connected by a bus structure in a tree-type arrangement that includes a front section, the front section having a series of multiple tiers of memory circuits in which, for each tier except the last in the series of the front section, the second set of bus connections of the memory circuits in each tier branches out and connects to the first set of bus connections of a set of one or more memory circuits of a subsequent tier in the series, and wherein the first set of bus connections of the one or more memory circuits of a first tier in the series is connected to a corresponding branch from an input bus section, the assigning of addresses including:
determining a tier address for each of the memory circuits by propagating a signal from the input bus section through the series of tiers according to a first clock, wherein the tier address is determined based upon a number of cycles of the first clock required for the signal to propagate to a corresponding memory circuit;
determining an intra-tier sub-address for each of the memory circuits of the front section by sequentially propagating a signal within each set of memory circuits branching out from a common memory circuit in the preceding tier according to a second clock, wherein the intra-tier address is determined based upon a number of cycles of the second clock required for the signal to propagate to a corresponding memory circuit; and
assigning an address to each of the memory circuits according to:
the corresponding determined tier address;
the corresponding intra-tier sub-address; and
for the memory circuits of the front section, the intra-tier sub-addresses for each preceding tier of the front section identifying the corresponding branch to which the memory circuit belongs.

13. The method of claim 12 , further comprising:
for each of the memory circuits, storing the corresponding assigned address in a register of the memory circuit.

14. The method of claim 13 , wherein the corresponding assigned addresses are stored in non-volatile memory.

15. The method of claim 12 , wherein the tree-type arrangement further includes a back section, the back section having a series of one or more tiers in which for each tier except the first tier in the series of the back section, the first set of bus connections of memory circuits in each tier branches in and connects to the second set of bus connections of a set one or more memory circuits of the preceding tier in the series of the back section, and where the second set of bus connections of the one of more memory circuits of the last tier in the series of the back section being connected to a

Assignees

• Sandisk Technologies Llc

Inventors

• Tam Eugene Jinglun

Classifications

• G11C29/88 Primary

  with partially good memories · CPC title

• G11C29/83

  with reduced power consumption · CPC title

• G11C8/12

  Group selection circuits, e.g. for memory block selection, chip selection, array selection · CPC title

• G11C5/00

  Details of stores covered by group G11C11/00 · CPC title

• G06F2212/2022

  Flash memory · CPC title