Disabling a command associated with a memory device

Patent metadata

Field	Value
Publication number	US-9740433-B2
Application number	US-201615358524-A
Country	US
Kind code	B2
Filing date	Nov 22, 2016
Priority date	Mar 31, 2014
Publication date	Aug 22, 2017
Grant date	Aug 22, 2017

Abstract

In an embodiment, a memory device may contain device processing logic and a mode register. The mode register may a register that may specify a mode of operation of the memory device. A field in the mode register may hold a value that may indicate whether a command associated with the memory device is disabled. The value may be held in the field until either the memory device is power-cycled or reset. The device processing logic may acquire an instance of the command. The device processing logic may determine whether the command is disabled based on the value held by the mode register. The device processing logic may not execute the instance of the command if the device processing logic determines the command is disabled. If the device processing logic determines the command is not disabled, the device processing logic may execute the instance of the command.

First claim

What is claimed is:

1. A memory device comprising:
memory cells;
a mode register to contain a value to indicate whether post package repair (PPR) is disabled for the memory device; and
device processing logic to:
receive a command to cause PPR, and
in response to receipt of the command, selectively cause or not cause PPR for one or more of the memory cells based in part on the value in the mode register.

2. The memory device of claim 1 , wherein the device processing logic is to:
not cause PPR based in part on a determination that the value in the mode register indicates PPR is disabled.

3. The memory device of claim 1 , wherein the device processing logic is to:
cause PPR based in part on a determination that the value in the mode register indicates PPR is not disabled.

4. The memory device of claim 1 , wherein the device processing logic is to:
in response to receipt of the command, remap a row of the memory cells based in part on a determination that the value in the mode register indicates that PPR is not disabled.

5. The memory device of claim 1 , wherein the device processing logic is to:
receive a second command and the value; and
responsive to receipt of the second command, store the value in the mode register.

6. The memory device of claim 1 , wherein the command is a vendor specific command.

7. The memory device of claim 1 , wherein responsive to an occurrence of an event to cause the command to no longer be disabled, a value that indicates the command is not disabled is stored in the mode register.

8. The memory device of claim 7 , wherein the event is a power-cycling of the memory device or a reset of the memory device.

9. The memory device of claim 1 , wherein the device processing logic includes the mode register.

10. The memory device of claim 1 , wherein the memory device comprises: a dynamic RAM (DRAM) device, flash memory device, static RAM (SRAM) device, zero-capacitor RAM (ZRAM) device, twin transistor RAM (TTRAM) device, read-only memory (ROM) device, ferroelectric transistor RAM (FeTRAM) device, magneto-resistive RAM (MRAM) device, phase change memory (PCM) device, PCM and switch (PCMS) device, nanowire-based device, resistive RAM memory (RRAM) device, or electrically erasable programmable ROM (EEPROM) device.

11. A memory device comprising:
memory cells;
a mode register to contain a value to indicate whether post package repair (PPR) is disabled for the memory device;
a means to receive a command to cause PPR; and
a means to, in response to receipt of the command, selectively cause or not cause PPR for one or more of the memory cells based in part on the value in the mode register.

12. The memory device of claim 11 , wherein the means to selectively cause or not cause PPR is to:
not cause PPR based in part on a determination that the value in the mode register indicates PPR is disabled.

13. The memory device of claim 11 , wherein the means to selectively cause or not cause PPR is to:
cause PPR based in part on a determination that the value in the mode register indicates PPR is not disabled.

14. The memory device of claim 11 , further comprising:
means to, in response to receipt of the command, remap a row of the memory cells based in part on a determination that the value in the mode register indicates that PPR is not disabled.

15. The memory device of claim 11 , further comprising:
means to receive a second command and the value; and
means to, in response to receipt of the second command, store the value in the mode register.

16. The memory device of claim 11 , wherein the command is a vendor specific command.

17. The memory device of claim 11 , wherein responsive to an occurrence of an event to cause the command to no longer be disabled, a value that indicates the command is not disabled is stored in the mode register.

18. The memory device of claim 17 , wherein the event is a power-cycling of the memory device or a reset of the memory device.

19. The memory device of claim 11 , wherein the memory device comprises: a dynamic RAM (DRAM) device, flash memory device, static RAM (SRAM) device, zero-capacitor RAM (ZRAM) device, twin transistor RAM (TTRAM) device, read-only memory (ROM) device, ferroelectric transistor RAM (FeTRAM) device, magneto-resistive RAM (MRAM) device, phase change memory (PCM) device, PCM and switch (PCMS) device, nanowire-based device, resistive RAM memory (RRAM) device, or electrically erasable programmable ROM (EEPROM) device.

20. A system comprising:
a memory controller;
a memory device communicatively coupled with the memory controller, wherein the memory device comprises:
a mode register to contain a value to indicate whether post package repair (PPR) is disabled for the memory device; and
device processing logic to:
receive a command from the memory controller to cause PPR, and
selectively cause or not cause PPR in response to receipt of the command based in part on the value in the mode register.

21. The system of claim 20 , further comprising a processor communicatively coupled with the memory device.

22. The system of claim 21 , wherein the processor includes the memory controller.

23. The system of claim 21 , further comprising a display communicatively coupled with the processor.

24. The system of claim 20 , wherein the device processing logic is to:
not cause PPR based in part on a determination that the value in the mode register indicates PPR is disabled.

25. The system of claim 20 , wherein the device processing logic is to:
cause PPR based in part on a determination that the value in the mode register indicates PPR is not disabled.

26. The system of claim 20 , wherein the device processing logic is to:
in response to receipt of the command, remap a row of memory cells based in part on a determination that the value in the mode register indicates that PPR is not disabled.

27. The system of claim 20 , wherein the device processing logic is to:
receive a second command and the value; and
responsive to receipt of the second command, store the value in the mode register.

28. The system of claim 20 , wherein the command is a vendor specific command.

29. The system of claim 20 , wherein responsive to an occurrence of an event to cause the command to no longer be disabled, a value that indicates the command is not disabled is stored in the mode register.

30. The system of claim 29 , wherein the event is a power-cycling of the memory device or a reset of the memory device.

31. The system of claim 20 , wherein the device processing logic includes the mode register.

32. The system of claim 20 , wherein the memory device comprises: a dynamic RAM (DRAM) device, flash memory device, static RAM (SRAM) device, zero-capacitor RAM (ZRAM) device, twin transistor RAM (TTRAM) device, read-only memory (ROM) device, ferroelectric transistor RAM (FeTRAM) device, magneto-resistive RAM (MRAM) device, phase change memory (PCM) device, PCM and switch (PCMS) device, nanowire-based device, resistive RAM memory (RRAM) device, or electrically erasable programmable ROM (EEPROM) device.

33. A method comprising:
receiving a command to cause post package repair (PPR) for one or more memory cells of a memory device;
determining whether PPR is disabled for the memory device b

Assignees

• Intel Corp

Inventors

• Mozak Christopher P
• Bains Kuljit S

Classifications

• G11C7/24 Primary

  Memory cell safety or protection circuits, e.g. arrangements for preventing inadvertent reading or writing; Status cells; Test cells · CPC title

• G06F3/0625

  Power saving in storage systems · CPC title

• G06F3/0673

  Single storage device · CPC title

• G11C29/46

  Test trigger logic · CPC title

• G11C29/70

  Masking faults in memories by using spares or by reconfiguring · CPC title