Power semiconductor package with conductive clip

US9118126B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9118126-B2
Application numberUS-201313739422-A
CountryUS
Kind codeB2
Filing dateJan 11, 2013
Priority dateMar 4, 2011
Publication dateAug 25, 2015
Grant dateAug 25, 2015

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  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

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  4. Key dates

    Filing, priority, publication, and grant dates set the timeline.

  5. First independent claim

    The legal scope of protection — read this for what is actually claimed.

  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

    Prior art links and similar publications in this corpus.

Abstract

Official abstract text for this publication.

According to one disclosed embodiment, a power semiconductor package includes an insulated-gate bipolar transistor (IGBT) residing on a package substrate, where the IGBT includes a plurality of solderable front metal (SFM) coated emitter segments situated atop the IGBT and connected to an emitter of the IGBT. The power semiconductor package also includes a conductive clip coupling the plurality of SFM coated emitter segments to an emitter pad on the package substrate. Additionally, the power semiconductor package includes a gate pad on the package substrate coupled to a gate of the IGBT, a collector pad on the package substrate situated under the IGBT and coupled to a collector of the IGBT, and an emitter terminal, a collector terminal and a gate terminal of the package substrate that are routed to the emitter pad, collector pad, and gate pad, respectively.

First claim

Opening claim text (preview).

The invention claimed is: 1. A power semiconductor package comprising: an insulated-gate bipolar transistor (IGBT)residing on a package substrate, said IGBT including a solderable front metal (SFM) coated emitter segment situated atop said IGBT and connected to an emitter of said IGBT, wherein said solderable front metal coated emitter segment includes a conductive layer and a solderable front metal layer coating said conductive layer; a conductive clip coupling said SFM coated emitter segment to an emitter pad on said package substrate; a gate pad on said package substrate coupled to a gate of said IGBT; a collector pad on said package substrate situated under said IGBT and coupled to a collector of said IGBT. 2. The power semiconductor package of claim 1 wherein an emitter terminal of said package substrate is routed to said emitter pad. 3. The power semiconductor package of claim 1 wherein a collector terminal of said package substrate is routed to said collector pad. 4. The power semiconductor package of claim 1 wherein a gate terminal of said package substrate is routed to said gate pad. 5. The power semiconductor package of claim 1 wherein said conductive clip comprises copper. 6. The power semiconductor package of claim 1 wherein said SFM coated emitter segment comprises a metal selected from the group consisting of Ti, Ni and Ag. 7. The power semiconductor package of claim 1 wherein said conductive clip is coupled to said emitter pad over substantially all of said emitter pad. 8. The power semiconductor package of claim 1 wherein said conductive clip is coupled to said SFM coated emitter segment over substantially all of a total surface area of said SFM coated emitter segment. 9. The power semiconductor package of claim 1 wherein said conductive clip is coupled to said emitter pad using a conductive adhesive. 10. The power semiconductor package of claim 1 wherein said conductive clip is coupled to said SFM coated emitter segment using a conductive adhesive. 11. The power semiconductor package of claim 1 wherein said conductive clip comprises at least one through-hole configured to allow reflow degassing. 12. The power semiconductor package of claim 1 wherein said conductive clip is configured to form a void between said emitter pad and said IGBT. 13. The power semiconductor package of claim 1 wherein said conductive clip comprises a conductive clip notch to allow coupling to said gate of said IGBT. 14. The power semiconductor package of claim 1 wherein said conductive clip comprises a conductive clip sensor finger configured to couple an emitter sensor pad on said package substrate to said emitter of said IGBT. 15. The power semiconductor package of claim 1 wherein said conductive clip comprises a substantially flat top surface for thermal sinking. 16. The power semiconductor package of claim 1 wherein said conductive clip comprises a conductive clip extension corresponding to said SFM coated emitter segment; said conductive clip extension configured to couple said SFM coated emitter segment to a conductive clip body of said conductive clip. 17. A conductive clip for an insulated-gate bipolar transistor (IGBT) package, said conductive clip comprising: a conductive clip extension coupled to an emitter segment of an IGBT, said emitter segment situated atop said IGBT and connected to an emitter of said IGBT, said IGBT residing on a package substrate; a conductive clip leg coupled to an emitter pad on said package substrate; a conductive clip body coupling said conductive clip extension to said conductive clip leg; wherein said solderable front metal coated emitter segment includes a solderable front metal layer over a conductive layer. 18. The conductive clip of claim 17 further comprising a collector pad on said package substrate situated under said IGBT and coupled to a collector of said IGBT. 19. The conductive clip of claim 17 wherein said conductive clip leg is electrically and mechanically coupled to said emitter pad. 20. The conductive clip of claim 17 wherein a thickness of said conductive clip leg and a thickness of said conductive clip body are configured to form a void between said emitter pad and said IGBT.

Assignees

Inventors

Classifications

  • between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

  • between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

  • between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

  • changes in shapes · CPC title

  • using a polymer adhesive, e.g. an adhesive based on silicone or epoxy · CPC title

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Frequently asked questions

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What does patent US9118126B2 cover?
According to one disclosed embodiment, a power semiconductor package includes an insulated-gate bipolar transistor (IGBT) residing on a package substrate, where the IGBT includes a plurality of solderable front metal (SFM) coated emitter segments situated atop the IGBT and connected to an emitter of the IGBT. The power semiconductor package also includes a conductive clip coupling the plurality…
Who is the assignee on this patent?
Int Rectifier Corp
What technology area does this patent fall under?
Primary CPC classification H10W90/701. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Aug 25 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).