Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with gate contact position and offset specifications

Patent metadata

Field	Value
Publication number	US-9117050-B2
Application number	US-201213591141-A
Country	US
Kind code	B2
Filing date	Aug 21, 2012
Priority date	Mar 13, 2008
Publication date	Aug 25, 2015
Grant date	Aug 25, 2015

Abstract

A semiconductor device includes conductive features that are each defined within any one gate level channel that is uniquely associated with and defined along one of a number of parallel gate electrode tracks. The conductive features form gate electrodes of first and second PMOS transistor devices, and first and second NMOS transistor devices. The gate electrodes of the first PMOS and first NMOS transistor devices extend along a first gate electrode track. The gate electrodes of the second PMOS and second NMOS transistor devices extend along a second gate electrode track. A first set of interconnected conductors electrically connect the gate electrodes of the first PMOS and second NMOS transistor devices. A second set of interconnected conductors electrically connect the gate electrodes of the second PMOS and first NMOS transistor devices. The first and second sets of interconnected conductors traverse across each other within different levels of the semiconductor device.

First claim

What is claimed is:

1. An integrated circuit, comprising:
a gate electrode level region having a number of adjacently positioned gate electrode feature layout channels, each gate electrode feature layout channel extending lengthwise in a first direction and widthwise in a second direction perpendicular to the first direction, wherein each of the number of adjacently positioned gate electrode feature layout channels includes at least one gate level feature, each gate level feature having a first end located adjacent to a first line end spacing and a second end located adjacent to a second line end spacing, wherein each gate level feature forms an electrically conductive path extending between its first and second ends,
wherein the gate electrode level region includes a first gate level feature that forms a gate electrode of a first transistor of a first transistor type and a gate electrode of a first transistor of a second transistor type,
wherein the gate electrode level region includes a second gate level feature that forms a gate electrode of a second transistor of the first transistor type, wherein any transistor having its gate electrode formed by the second gate level feature is of the first transistor type,
wherein the gate electrode level region includes a third gate level feature that forms a gate electrode of a second transistor of the second transistor type, wherein any transistor having its gate electrode formed by the third gate level feature is of the second transistor type,
wherein the gate electrode of the second transistor of the second transistor type is substantially co-aligned with the gate electrode of the second transistor of the first transistor type along a first common line of extent in the first direction, and wherein the third gate level feature is separated from the second gate level feature by a first line end spacing as measured in the first direction,
wherein the gate electrode level region includes a fourth gate level feature that forms a gate electrode of a third transistor of the first transistor type, wherein any transistor having its gate electrode formed by the fourth gate level feature is of the first transistor type,
wherein the gate electrode level region includes a fifth gate level feature that forms a gate electrode of a third transistor of the second transistor type, wherein any transistor having its gate electrode formed by the fifth gate level feature is of the second transistor type,
wherein the gate electrode of the third transistor of the second transistor type is substantially co-aligned with the gate electrode of the third transistor of the first transistor type along a second common line of extent in the first direction, and wherein the fifth gate level feature is separated from the fourth gate level feature by a second line end spacing as measured in the first direction,
wherein the gate electrode level region includes a sixth gate level feature that forms a gate electrode of a fourth transistor of the first transistor type and a gate electrode of a fourth transistor of the second transistor type,
wherein the gate electrodes of the second and third transistors of the first transistor type are positioned between the gate electrodes of the first and fourth transistors of the first transistor type in the second direction, and
wherein the gate electrodes of the second and third transistors of the second transistor type are positioned between the gate electrodes of the first and fourth transistors of the second transistor type in the second direction;
a first gate contact defined to physically contact the second gate level feature;
a second gate contact defined to physically contact the third gate level feature;
a third gate contact defined to physically contact the fourth gate level feature;
a fourth gate contact defined to physically contact the fifth gate level feature; and
wherein the first, second, third, and fourth transistors of the first transistor type are collectively separated from the first, second, third, and fourth transistors of the second transistor type by an inner portion of the gate electrode level region,
wherein first, second, third, and fourth gate contacts are respectively positioned over the inner portion of the gate electrode level region,
wherein the second and third gate contacts are offset from each other in the first direction, and
wherein either a) the first and third gate contacts are offset from each other in the first direction, or b) the second and fourth gate contacts are offset from each other in the first direction.

2. An integrated circuit as recited in claim 1 , wherein the gate electrodes of the first, second, third, and fourth transistors of the first transistor type are positioned according to a gate pitch such that a distance measured in the second direction between first-direction-oriented centerlines of any two of the gate electrodes of the first, second, third, and fourth transistors of the first transistor type is substantially equal to an integer multiple of the gate pitch, and
wherein the gate electrodes of the first, second, third, and fourth transistors of the second transistor type are positioned according to the gate pitch such that a distance measured in the second direction between first-direction-oriented centerlines of any two of the gate electrodes of the first, second, third, and fourth transistors of the second transistor type is substantially equal to an integer multiple of the gate pitch.

3. An integrated circuit as recited in claim 2 , wherein the gate electrode level region includes a seventh gate level feature that forms a gate electrode of a fifth transistor of the first transistor type and a gate electrode of a fifth transistor of the second transistor type.

4. An integrated circuit as recited in claim 3 , wherein all gate level features within the gate electrode level region are linear shaped and extend lengthwise in the first direction.

5. An integrated circuit as recited in claim 4 , wherein the gate electrode level region includes an eighth gate level feature that does not form a gate electrode of a transistor, the eighth gate level feature positioned such that a distance as measured in the second direction between a first-direction-oriented centerline of the eighth gate level feature and a first-direction-oriented centerline of a gate electrode of a transistor within the gate electrode level region is substantially equal to an integer multiple of the gate pitch.

6. An integrated circuit as recited in claim 1 , wherein the second gate level feature has an extension distance extending away from the first gate contact in the first direction away from the gate electrode of the second transistor of the first transistor type,
wherein the third gate level feature has an extension distance extending away from the second gate contact in the first direction away from the gate electrode of the second transistor of the second transistor type,
wherein the fourth gate level feature has an extension distance extending away from the third gate contact in the first direction away from the gate electrode of the third transistor of the first transistor type,
wherein the fifth gate level feature has an extension distance extending away from the fourth gate contact in the first direction away from the gate electrode of the third transistor of the second transistor type, and
wherein at least two of the extension distances of the second, third, fourth, and fifth gate level features are different.

7. An integrated circuit as recited in claim 6 , wherein two of the second, third, fourth, and fifth gate level features has a different length as measured in the first direction.

8. An integrated circuit as recited in claim 7 , wherein all gate electrode

Assignees

• Becker Scott T
• Mali Jim
• Lambert Carole
• Tela Innovations Inc

Inventors

• Becker Scott T
• Mali Jim
• Lambert Carole

Classifications

• H10W70/611

  for connecting multiple chips together · CPC title

• H10W70/65

  Shapes or dispositions of interconnections · CPC title

• H10W70/658

  for devices provided for in groups H10D8/00 - H10D48/00 · CPC title

• G06F30/39

  Circuit design at the physical level (physical level design for reconfigurable circuits G06F30/347) · CPC title

• G06F30/392

  Floor-planning or layout, e.g. partitioning or placement · CPC title