Strained channel dynamic random access memory devices

Patent metadata

Field	Value
Publication number	US-9153591-B2
Application number	US-201414533964-A
Country	US
Kind code	B2
Filing date	Nov 5, 2014
Priority date	Aug 13, 2001
Publication date	Oct 6, 2015
Grant date	Oct 6, 2015

Abstract

DRAM trench capacitors formed by, inter alia, deposition of conductive material into a trench or doping the semiconductor region in which the trench is defined.

First claim

What is claimed is:

1. A structure comprising:
a substrate having a first region and a second region;
a graded layer on the substrate in the first region;
a relaxed layer on the graded layer;
a strained layer on the relaxed layer, a recess being in the strained layer and the relaxed layer in the first region; and
a capacitor defined in the recess, the capacitor comprising a first conductive plate along a sidewall of the recess, an insulating material on the first conductive plate, and a second conductive plate on the insulating material.

2. The structure of claim 1 further comprising a device in the second region of the substrate, at least a portion of the device comprising a portion of the strained semiconductor material, the device being electrically coupled to the capacitor.

3. The structure of claim 1 , wherein the recess is further in the graded layer in the first region.

4. The structure of claim 1 , wherein the recess is further in the graded layer in the first region and in the substrate in the first region.

5. The structure of claim 1 , wherein the strained layer is tensilely strained.

6. The structure of claim 1 , wherein the first conductive plate comprises a doped portion of the sidewall of the recess.

7. A structure comprising:
a memory cell comprising:
a capacitor disposed in a recess, the recess extending in a strained layer and a relaxed layer, the relaxed layer being over a semiconductor substrate, the strained layer being over the relaxed layer; and
an access transistor electrically coupled to the capacitor, a channel of the access transistor being disposed in the strained layer.

8. The structure of claim 7 , wherein the memory cell is a Dynamic Random Access Memory (DRAM) cell.

9. The structure of claim 7 , wherein the capacitor comprises a first conductive plate along a sidewall of the recess, an insulating material on the first conductive plate, and a second conductive plate on the insulating material.

10. The structure of claim 9 , wherein the insulating material has a dielectric constant greater than a dielectric constant of silicon dioxide.

11. The structure of claim 9 , wherein the first conductive plate comprises at least a doped portion of the sidewall of the recess.

12. The structure of claim 7 , wherein a graded layer is over the semiconductor substrate, the relaxed layer being over the graded layer.

13. The structure of claim 12 , wherein the recess further extends in the graded layer.

14. The structure of claim 12 , wherein the recess further extends in the graded layer and the semiconductor substrate.

15. The structure of claim 7 , wherein the strained layer is tensilely strained.

16. A method comprising:
forming a relaxed layer over a semiconductor substrate;
forming a strained layer over the relaxed layer;
forming a recess in the relaxed layer and the strained layer; and
forming a capacitor in the recess, the forming the capacitor comprising:
forming a first plate along a sidewall of the recess,
forming an insulating layer along the first plate, and
forming a second plate along the insulating layer.

17. The method of claim 16 , wherein the forming the insulating layer comprises depositing a material with a dielectric constant greater than silicon dioxide.

18. The method of claim 16 , wherein the forming the first plate comprises implanting the sidewall of the recess with a dopant.

19. The method of claim 16 , wherein the forming the first plate comprises depositing a sacrificial material and out-diffusing a dopant from the sacrificial material into the sidewall of the recess.

20. The method of claim 16 further comprising:
forming a graded layer over the semiconductor substrate, the relaxed layer being formed over the graded layer, the recess being formed in the graded layer and in the semiconductor substrate; and
forming a device having a channel disposed in the strained layer, the device being electrically coupled to the capacitor.

Assignees

• Taiwan Semiconductor Mfg

Inventors

• Bulsara Mayank T
• Currie Matthew T
• Lochtefeld Anthony J

Classifications

• H10D30/798

  being provided in or under the channel regions · CPC title

• H10D30/751

  having composition variations in the channel regions · CPC title

• H10D1/665 Primary

  Trench conductor-insulator-semiconductor capacitors, e.g. trench MOS capacitors · CPC title

• H10D1/68

  Capacitors having no potential barriers · CPC title

• H01L27/1087

  Electricity · mapped topic