Apparatus for manufacturing semiconductor devices

US9138980B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9138980-B2
Application numberUS-201213624470-A
CountryUS
Kind codeB2
Filing dateSep 21, 2012
Priority dateJun 22, 2010
Publication dateSep 22, 2015
Grant dateSep 22, 2015

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

The present invention relates to an apparatus for the manufacture of semiconductor devices wherein the apparatus includes a bonding module that has a vacuum chamber to provide bonding of wafers under pressure below atmospheric pressure; and a loadlock module connected to the bonding module and configured for wafer transfer to the bonding module. The loadlock module is also connected to a first vacuum pumping device configured to reduce the pressure in the loadlock module to below atmospheric pressure. The bonding and loadlock modules remain at a pressure below atmospheric pressure while the wafer is transferred from the loadlock module into the bonding module.

First claim

Opening claim text (preview).

What is claimed is: 1. An apparatus for the molecular bonding of semiconductor devices, the apparatus comprising: a bonding module comprising a vacuum chamber to provide bonding of a first wafer and a second wafer under a pressure below atmospheric pressure, and at least a first bonding chuck and a second bonding chuck configured to hold the first wafer and the second wafer, respectively, with the main surfaces of the first and second wafers arranged face-to-face in vertical orien…

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What does patent US9138980B2 cover?
The present invention relates to an apparatus for the manufacture of semiconductor devices wherein the apparatus includes a bonding module that has a vacuum chamber to provide bonding of wafers under pressure below atmospheric pressure; and a loadlock module connected to the bonding module and configured for wafer transfer to the bonding module. The loadlock module is also connected to a first …
Who is the assignee on this patent?
Soitec Silicon On Insulator
What technology area does this patent fall under?
Primary CPC classification H10P72/0428. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Sep 22 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).