Wafer processing method
US-2024395620-A1 · Nov 28, 2024 · US
Substrateless power device packages
US9136154B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9136154-B2 |
| Application number | US-201414533366-A |
| Country | US |
| Kind code | B2 |
| Filing date | Nov 5, 2014 |
| Priority date | Oct 29, 2010 |
| Publication date | Sep 15, 2015 |
| Grant date | Sep 15, 2015 |
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- Title
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Abstract
Official abstract text for this publication.
A substrate-less composite power semiconductor device may be fabricated from a vertical conductive power semiconductor device wafer that includes a top metal layer located on a top surface of the wafer by a) forming solder bumps on top of the top metal layer; b) forming wafer level molding around the solder bumps such that the solder bumps are exposed through a top of the wafer level molding; c) grinding a back side of the device wafer to reduce a total thickness of a semiconductor material portion of the device wafer to a final thickness; and d) forming a back metal on a back surface of the wafer.
First claim
Opening claim text (preview).
What is claimed is: 1. A method for making a power semiconductor device, comprising: a) forming solder bumps on top of a top metal layer of a vertical conductive power semiconductor device wafer having the top metal layer located on a top surface of the wafer; b) forming a wafer level molding around the solder bumps, wherein the solder bumps extend above a top surface of the wafer level molding; c) grinding a back side of the device wafer to reduce a total thickness of a semic…
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Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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Frequently asked questions
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- What does patent US9136154B2 cover?
- A substrate-less composite power semiconductor device may be fabricated from a vertical conductive power semiconductor device wafer that includes a top metal layer located on a top surface of the wafer by a) forming solder bumps on top of the top metal layer; b) forming wafer level molding around the solder bumps such that the solder bumps are exposed through a top of the wafer level molding; c…
- Who is the assignee on this patent?
- Alpha & Omega Semiconductor
- What technology area does this patent fall under?
- Primary CPC classification H10P72/7402. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Sep 15 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).