Self-aligned double spacer patterning process

Patent metadata

Field	Value
Publication number	US-9123776-B2
Application number	US-201314096963-A
Country	US
Kind code	B2
Filing date	Dec 4, 2013
Priority date	Dec 4, 2013
Publication date	Sep 1, 2015
Grant date	Sep 1, 2015

Abstract

Embodiments of the present disclosure are a method of forming a semiconductor device and methods of patterning a semiconductor device. An embodiment is a method of forming a semiconductor device, the method including forming a first hard mask layer over a semiconductor device layer, forming a set of mandrels over the first hard mask layer, and forming a first spacer layer over the set of mandrels and the first hard mask layer. The method further includes forming a second spacer layer over the first spacer layer, patterning the first spacer layer and the second spacer layer to form a mask pattern, and patterning the first hard mask layer using the mask pattern as a mask.

First claim

What is claimed is:

1. A method of forming a semiconductor device, the method comprising:
forming a first hard mask layer over a semiconductor device layer;
forming a set of mandrels over the first hard mask layer;
forming a first spacer layer over the set of mandrels and the first hard mask layer;
forming a second spacer layer over the first spacer layer;
patterning the first spacer layer and the second spacer layer to form a mask pattern, the patterning further comprisin…

Assignees

• Taiwan Semiconductor Mfg

Inventors

• Tsai Cheng-Hsiung
• Wu Yung-Hsu
• Huang Tsung-Min
• Lee Chung-Ju
• Bao Tien-I
• Shue Shau-Lin

Classifications

• H10P76/4088

  Electricity · mapped topic

• H10P76/4085

  Electricity · mapped topic

• H10P76/405 Primary

  Electricity · mapped topic

• H10P76/204

  Electricity · mapped topic

• H10P50/696

  Electricity · mapped topic