Process for forming package-on-package structures
US-8975741-B2 · Mar 10, 2015 · US
US9123763B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9123763-B2 |
| Application number | US-201113271952-A |
| Country | US |
| Kind code | B2 |
| Filing date | Oct 12, 2011 |
| Priority date | Oct 12, 2011 |
| Publication date | Sep 1, 2015 |
| Grant date | Sep 1, 2015 |
A practical reading order for non-experts. Skip the full description unless you need deep technical detail.
What the patent document calls the invention.
A short plain-language summary of the technical disclosure.
Who owns or filed the patent and who is credited as inventor.
Filing, priority, publication, and grant dates set the timeline.
The legal scope of protection — read this for what is actually claimed.
Technology tags used to group this patent with similar filings.
Prior art links and similar publications in this corpus.
Official abstract text for this publication.
A package-on-package (PoP) structure comprises a first package and a second package. The first package comprises a first die, a second die, and a core material. The core material has a first surface and a second surface. A first redistribution layer (RDL) is on the first surface, and a second RDL is on the second surface. The first die is disposed in the core material between the first surface and the second surface. The second die is coupled to one of the first RDL and the second RDL. The second package comprises a third die and an interposer. The interposer has a first side and a second side. The third die is coupled to the second side of the interposer. The first package is coupled to the second package by first electrical connectors coupled to the second side of the interposer and the first RDL.
Opening claim text (preview).
What is claimed is: 1. A package-on-package (PoP) structure comprising: an interposer having a semiconductor substrate with a first side and a second side opposite the first side, through substrate vias through the semiconductor substrate electrically coupling a first metallization pattern on the first side of the semiconductor substrate to a second metallization pattern on a second side of the semiconductor substrate; a first die on the second side of the interposer and coupled…
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Related publications grouped by family.
Free tools are coming soon. Tell us what you want to track and we'll notify you.
Answers are generated from the same data shown on this page.