Semiconductor die, semiconductor package and substrate dicing method
US-2024421000-A1 · Dec 19, 2024 · US
US9105708B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9105708-B2 |
| Application number | US-201314013965-A |
| Country | US |
| Kind code | B2 |
| Filing date | Aug 29, 2013 |
| Priority date | Sep 10, 2012 |
| Publication date | Aug 11, 2015 |
| Grant date | Aug 11, 2015 |
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Official abstract text for this publication.
A wafer processing method divides a wafer along a plurality of crossing streets formed on the front side of the wafer to thereby partition a plurality of regions where a plurality of devices are respectively formed. The method includes a division groove forming step of cutting the back side of the wafer along each street by using a cutting blade to thereby form a division groove along each street with a predetermined thickness left between the bottom of the division groove and the front side of the wafer, a wafer supporting step of attaching the back side of the wafer to a dicing tape supported by an annular frame, and a wafer dividing step of applying an external force to the wafer attached to the dicing tape to thereby divide the wafer into the individual devices along the streets where the division grooves are respectively formed.
Opening claim text (preview).
What is claimed is: 1. A wafer processing method of dividing a wafer formed of a wafer material along a plurality of crossing streets formed on the front side of said wafer to thereby partition a plurality of regions where a plurality of devices are respectively formed, said wafer processing method comprising: a protective member attaching step of attaching a protective member to the front side of said wafer; a division groove forming step of cutting the back side of said wafer…
Electricity · mapped topic
Electricity · mapped topic
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