Write and read collision avoidance in single port memory devices

Patent metadata

Field	Value
Publication number	US-8995210-B1
Application number	US-201314090060-A
Country	US
Kind code	B1
Filing date	Nov 26, 2013
Priority date	Nov 26, 2013
Publication date	Mar 31, 2015
Grant date	Mar 31, 2015

Abstract

A method of avoiding a write collision in single port memory devices from two or more independent write operations is described. A first write operation having a first even data object and a first odd data object is received from a first data sender. A second write operation having a second even data object and a second odd data object is received from a second data sender at substantially the same time as the first write operation. The second write operation is delayed so that the first even data object writes to a first single port memory device at a different time than the second even data object writes to the first single port memory device. The second write operation is delayed so that the first odd data object writes to a second single port memory device at a different time than the second odd data object.

First claim

What is claimed is:

1. A method of avoiding a write collision in single port memory devices from two or more independent write operations, comprising:
receiving, by a module, a first write operation having a first even data object and a first odd data object from a first data sender,
receiving, by the module, a second write operation having a second even data object and a second odd data object from a second data sender at substantially a same time as the first write operation;
delaying the second write operation so that the first even data object writes to a first single port memory device at a different time than the second even data object writes to the first single port memory device, and delaying the second write operation so that the first odd data object writes to a second single port memory device at a different time than the second odd data object; and
writing the first even data object and first odd data object to respective first and second single port memory devices and writing the second even data object and second odd data object to the respective first and second single port memory devices.

2. The method of claim 1 , wherein the first data sender and second data sender are configured to align the first write operation and second write operation so that they are received by the module at substantially a same time.

3. The method of claim 1 , wherein the first data sender and the second data sender are cache memories.

4. The method of claim 1 , wherein the first odd data object is written to the first single port memory device at substantially a same time as the second even data object is written to the second single port memory device.

5. The method of claim 1 , wherein the first single port memory device and the second single port memory device include an upper half single port memory device and a lower half single port memory device to store a highest order bits address of data objects in the upper half and a lowest order bit address of the data objects in the lower half.

6. The method of claim 1 , wherein the single port memory devices are single port static random access memory (SRAM).

7. The method of claim 1 , further comprising:
receiving a read request for the first even data object from a first read requester;
reading an upper half of the first even data object from an upper half of the first single port memory device;
reading a lower half of the first even data object from a lower half of first single port memory device at substantially a same time as reading the upper half of the first even data object; and
combining the upper half and lower half of the first even data object to obtain the first data object, which is sent to the read requester.

8. The method of claim 1 , further comprising:
receiving a first read request for the first even data object and the first odd data object from a first read requester;
receiving a second read request for the second even data object and second odd data object from a second read requester at substantially a same time as receiving the first read request;
reading the first even data object from the first single port memory device;
reading the second odd data object from the second single port memory device at substantially a same time as reading the first even data object from the first single port memory device;
reading the second even data object from the first single port memory device; and
reading the first odd data object from the second single port memory device at substantially a same time as reading the second even data object from the first single port memory device.

9. A semiconductor chip, comprising:
a module, comprising:
a first single port memory device configured to store a first even data object and a second even data object,
a second single port memory device configured to store a first odd data object and a second odd data object, and
the module configured to:
receive a first write operation having a first even data object and a first odd data object from a first data sender,
receive a second write operation having a second even data object and a second odd data object from a second data sender at substantially a same time as the first write operation;
delay the second write operation so that the first even data object writes to a first single port memory device at a different time than the second even data object writes to the first single port memory device, and delay the second write operation so that the first odd data object writes to a second single port memory device at a different time than the second odd data object; and
write the first even data object and first odd data object to respective first and second single port memory devices and write the second even data object and second odd data object to the respective first and second single port memory devices.

10. The semiconductor chip of claim 9 , wherein the first data sender and second data sender are configured to align the first write operation and second write operation so that they are received by the module at substantially a same time.

11. The semiconductor chip of claim 9 , wherein the first data sender and the second data sender are cache memories.

12. The semiconductor chip of claim 9 , wherein the module further comprises:
a read controller configured to:
receive a read request for the first even data object from a first read requester;
read an upper half of the first even data object from an upper half of the first single port memory device;
read a lower half of the first even data object from a lower half first single port memory device at substantially a same time as reading the upper half of the first even data object; and
combine the upper half and lower half of the first even data object to obtain the first data object, which is sent to the read requester.

13. The semiconductor chip of claim 9 , wherein the module further comprises:
a read controller configured to:
receive a first read request for the first even data object and the first odd data object from a first read requester;
receive a second read request for the second even data object and second odd data object from a second read requester at substantially a same time as receiving the first read request;
read the first even data object from the first single port memory device;
read the second odd data object from the second single port memory device at substantially a same time as reading the first even data object from the first single port memory device;
read the second even data object from the first single port memory device; and
read the first odd data object from the second single port memory device at substantially a same time as reading the second even data object from the first single port memory device.

14. The semiconductor chip of claim 9 , wherein the first odd data object is written to the first single port memory device at substantially a same time as the second even data object is written to the second single port memory device.

15. The semiconductor chip of claim 9 , wherein the first single port memory device and the second single port memory device include an upper half single port memory device and a lower half single port memory device to store a highest order bits address of data objects in the upper half and a lowest order bit address of the data objects in the lower half.

16. The semiconductor chip of claim 9 , wherein the single port memory device is a single port static random access memory (SRAM).

17. A method of avoiding read collisions from single port memory devices from two or more inde

Assignees

• IBM

Inventors

• Hagspiel Norbert
• Junghans Sascha
• Klein Matthias
• Walter Joerg

Classifications

• G11C7/1015 Primary

  Read-write modes for single port memories, i.e. having either a random port or a serial port · CPC title

• G11C2207/2209

  Concurrent read and write · CPC title

• G11C7/1075 Primary

  for multiport memories each having random access ports and serial ports, e.g. video RAM · CPC title

• G11C7/222 Primary

  Clock generating, synchronizing or distributing circuits within memory device · CPC title