Nonvolatile memory interface for metadata shadowing

Patent metadata

Field	Value
Publication number	US-2016291870-A1
Application number	US-201514747976-A
Country	US
Kind code	A1
Filing date	Jun 23, 2015
Priority date	Apr 1, 2015
Publication date	Oct 6, 2016
Grant date	—

Abstract

A memory includes non-volatile memory devices, each of which has multiple nonvolatile memory cells. A write controller streams bits to the memory devices in groups of N bits using a write data channel having write bus drivers, receivers and write bus topology that take advantage of high-speed signaling to optimize a speed of writing to the memory devices. Consecutive groups of bits are written to consecutive memory cells within respective memory devices. A self-referenced read controller reads bits from the memory devices using a read channel having read drivers, receivers, and read bus topology that include no design requirements for high-speed or low-latency data transmission.

First claim

1 . A method for memory management, comprising:
streaming N bits to a memory buffer on a memory device using a write data channel having write bus drivers, receivers and write bus topology that optimize a speed of writing to the memory devices; writing the N bits to consecutive non-volatile memory cells in the memory device at a first speed, using a bi-directional bus; and reading bits from the memory device using self-referenced reads over a read channel having read drivers, receivers, and read bus topology to provide reads at a second speed that is slower than the first speed, using the bi-directional bus.

2 . The method of claim 1 , wherein reading bits from the memory devices is controlled and performed through a single read pin for all of the memory devices.

3 . The method of claim 1 , wherein the memory devices are connected in a daisy-chained fashion, wherein each device communicates via a first bus to a previous device in the chain and wherein each device communicates via a second bus to a subsequent device in the chain.

4 . The method of claim 1 , wherein all of the memory devices are connected by means of a common, ganged bus.

5 . The method of claim 1 , wherein performing self-referenced reads comprises:
reading a stored state of the memory cells; writing a reference state to the memory cells; reading the reference state of the memory cells; and for each memory cell, comparing the stored state to the reference state to determine a stored bit.

6 . The method of claim 1 , wherein reading bits is performed only after a fault has occurred.

7 . The method of claim 1 , wherein the memory device is a staging buffer for metadata.

8 . The method of claim 1 , wherein a read data channel's driver comprises an uncalibrated, minimum-strength, pulldown-only field effect transistor.

9 . The memory of claim 1 , wherein the write channel is ganged bus with a single trunk line and with impedance-matched termination on the far end of the trunk line from the write driver.

Assignees

• IBM

Inventors

• Debrosse John K
• Fitch Blake G
• Franceschini Michele M
• Takken Todd E
• Worledge Daniel C

Classifications

• G11C13/0069

  Writing or programming circuits or methods · CPC title

• G11C13/0061

  Timing circuits or methods · CPC title

• G06F3/0602 Primary

  specifically adapted to achieve a particular effect · CPC title

• G06F3/0613 Primary

  in relation to throughput · CPC title

• G11C7/10

  Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers · CPC title