Multi-chip package and memory system

Patent metadata

Field	Value
Publication number	US-9355685-B2
Application number	US-201514590626-A
Country	US
Kind code	B2
Filing date	Jan 6, 2015
Priority date	Mar 23, 2012
Publication date	May 31, 2016
Grant date	May 31, 2016

Abstract

A multi-chip package includes a first group of memory chips that includes a first memory chip and a second memory chip, a second group of memory chips that includes at least one memory chip, a first internal wiring system that couples the first memory chip and the second memory chip to a first terminal configured to receive a chip-enable signal, a second internal wiring system that couples the at least one memory chip to a second terminal configured to receive the chip-enable signal. The first memory chip and the second memory chip each include a chip address memory region configured to store an address associated with the memory chip, and an address rewrite module configured to rewrite the address associated with the memory chip and stored in the chip address memory region in response to an external operation.

First claim

What is claimed:

1. A memory system comprising:
a first memory chip;
a second memory chip;
a first wiring that couples the first memory chip to a first terminal through which a chip-enable signal is received; and
a second wiring that couples the second memory chip to a second terminal through which a chip-enable signal is received,
wherein the first memory chip comprises a chip address memory region configured to store an address, and a write module configured to write the address into the chip address memory region based on an external operation.

2. The memory system according to claim 1 , wherein the first memory chip includes an initial value-setting module configured to set the address associated with the memory chip to an initial state.

3. The memory system according to claim 2 , wherein the first memory chip includes address-setting pins and the initial value-setting module is configured to set the initial state of the address based on voltages applied to the address-setting pins.

4. The memory system according to claim 3 , wherein one of the address-setting pins is configured to couple the memory chip to a supply voltage and another of the address-setting pins is configured to be coupled to a ground voltage.

5. The memory system according to claim 2 , wherein the chip address memory region includes a nonvolatile memory and the initial value-setting module is configured to set the initial state of the address based on a value stored in the nonvolatile memory.

6. The memory system according to claim 1 , wherein the first terminal is configured to couple the first memory chip to a transfer controller.

7. The memory system according to claim 6 , wherein the first terminal and the second terminal are electrically coupled so that the first memory chip and the memory chip are each configured to receive the same chip-enable signal.

8. The memory system according to claim 6 , wherein the first terminal and the second terminal are independently coupled to the transfer controller of the memory system so that the first memory chip and the second memory chip each receive separate chip-enable signals.

9. The memory system according to claim 1 , wherein the first wiring includes at least one of an input/output signal line, a control signal line, and a ready/busy signal line.

10. A memory system comprising:
a first memory connected to a first terminal through which a chip-enable signal is received; and
a second memory connected to a second terminal through which a chip-enable signal is received,
wherein chip identification information is written into a memory region of the first memory based on an external operation.

Assignees

• Toshiba Kk

Inventors

• Matsunaga Naoki

Classifications

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/732

  between stacked chips · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W72/884

  Die-attach connectors and bond wires · CPC title

• G11C5/06 Primary

  Arrangements for interconnecting storage elements electrically, e.g. by wiring · CPC title