Nonvolatile memory interface for metadata shadowing

Patent metadata

Field	Value
Publication number	US-2016293241-A1
Application number	US-201514676292-A
Country	US
Kind code	A1
Filing date	Apr 1, 2015
Priority date	Apr 1, 2015
Publication date	Oct 6, 2016
Grant date	—

Abstract

A memory includes non-volatile memory devices, each of which has multiple nonvolatile memory cells. A write controller streams bits to the memory devices in groups of N bits using a write data channel having write bus drivers, receivers and write bus topology that take advantage of high-speed signaling to optimize a speed of writing to the memory devices. Consecutive groups of bits are written to consecutive memory cells within respective memory devices. A self-referenced read controller reads bits from the memory devices using a read channel having read drivers, receivers, and read bus topology that include no design requirements for high-speed or low-latency data transmission.

First claim

1 . A memory, comprising:
a plurality of non-volatile memory devices, each comprising a plurality of nonvolatile memory cells; a write controller configured to stream bits to the memory devices in groups of N bits using a write data channel having write bus drivers, receivers and write bus topology that optimize a speed of writing to the memory devices to provide writes at a first speed, wherein consecutive groups of bits are written to consecutive memory cells within respective memory devices; a self-referenced read controller configured to read bits from the memory devices using a read channel having read drivers, receivers, and read bus topology that include no design requirements for speed or latency of data transmission to provide reads at a second speed that is slower than the first speed; and a bi-directional bus that both the write controller and the self-referenced read controller share to access the plurality of non-volatile memory devices.

2 . The memory of claim 1 , wherein the read controller is configured to read bits from the memory devices, such that the read controller has a single read pin to control a read operation for all of the memory devices.

3 . The memory of claim 1 , wherein the memory devices are connected in a daisy-chained fashion, wherein each device communicates via a first bus to a previous device in the chain and wherein each device communicates via a second bus to a subsequent device in the chain.

4 . The memory of claim 1 , wherein the self-referenced read controller is configured to read a stored state of the memory cells in the memory devices, to write a reference state to the memory cells, to read the reference state of the memory cells, and for each memory cell to compare the stored state to the reference state to determine a stored bit.

5 . The memory of claim 1 , wherein the self-referenced read controller is configured to perform a read only after a fault has occurred.

6 . The memory of claim 1 , wherein the plurality of non-volatile memory devices are a staging buffer for metadata.

7 . The memory of claim 1 , wherein the non-volatile memory devices are magnetoresistive random access memory devices.

8 . The memory of claim 1 , wherein the non-volatile memory devices are phase change memory devices.

9 . The memory of claim 1 , wherein each memory device comprises an uncalibrated, minimum-strength, pulldown-only field effect transistor as a read driver.

10 . The memory of claim 1 , wherein the write bus is ganged bus with a single trunk line and with impedance-matched termination on the far end of the trunk line from the write driver.

11 - 19 . (canceled)

20 . A non-transitory computer readable storage medium comprising a computer readable program for memory management, wherein the computer readable program when executed on a computer causes the computer to perform the steps of:
streaming N bits to a memory buffer on a memory device using a write data channel having write bus drivers, receivers, and write bus topology that optimizes the speed of writing to the memory devices; writing the N bits to consecutive non-volatile memory cells in the memory device at a first speed; reading bits from the memory devices, at a second speed that is slower than the first speed, using a read data channel having read drivers, receivers, and read bus topology that include no design requirements for speed or latency of data transmission.

Assignees

• IBM

Inventors

• Debrosse John K
• Fitch Blake G
• Franceschini Michele M
• Takken Todd E
• Worledge Daniel C

Classifications

• G11C11/1693

  Timing circuits or methods · CPC title

• G11C13/0061

  Timing circuits or methods · CPC title

• G11C13/0004

  comprising amorphous/crystalline phase transition cells · CPC title

• G11C13/0069

  Writing or programming circuits or methods · CPC title

• G11C11/1675 Primary

  Writing or programming circuits or methods · CPC title