Method for fabricating three-dimensional semiconductor device using buried stop layer in substrate
US-2024268119-A1 · Aug 8, 2024 · US
Method for protection of a layer of a vertical stack and corresponding device
US8975730B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8975730-B2 |
| Application number | US-201213622573-A |
| Country | US |
| Kind code | B2 |
| Filing date | Sep 19, 2012 |
| Priority date | Sep 20, 2011 |
| Publication date | Mar 10, 2015 |
| Grant date | Mar 10, 2015 |
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Abstract
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A device and corresponding fabrication method includes a vertical stack having an intermediate layer between a lower region and an upper region. The intermediate layer is extended by a protection layer. The vertical stack has a free lateral face on which the lower region, the upper region and the protection layer are exposed.
First claim
Opening claim text (preview).
That which is claimed: 1. A device comprising: a vertical stack comprising a first silicon substrate, a second silicon substrate, and at least one intermediate layer between said first silicon substrate and second silicon substrate; said vertical stack comprising at least one free lateral face on which said first and second silicon substrates are exposed; and said vertical stack comprising a protection material in a cavity adjacent said at least one intermediate layer, with sa…
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Classifications
Electricity · mapped topic
- H10P90/1914Primary
Electricity · mapped topic
- H10W20/023Primary
Electricity · mapped topic
Electricity · mapped topic
- H01L21/76898Primary
Electricity · mapped topic
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- What does patent US8975730B2 cover?
- A device and corresponding fabrication method includes a vertical stack having an intermediate layer between a lower region and an upper region. The intermediate layer is extended by a protection layer. The vertical stack has a free lateral face on which the lower region, the upper region and the protection layer are exposed.
- Who is the assignee on this patent?
- St Microelectronics Crolles 2, St Microelectronics Sa
- What technology area does this patent fall under?
- Primary CPC classification H10P90/1914. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Mar 10 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).