Wafer processing method
US-2024395620-A1 · Nov 28, 2024 · US
Method for manufacturing electronic component
US8975347B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8975347-B2 |
| Application number | US-201113820871-A |
| Country | US |
| Kind code | B2 |
| Filing date | Sep 14, 2011 |
| Priority date | Oct 14, 2010 |
| Publication date | Mar 10, 2015 |
| Grant date | Mar 10, 2015 |
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- Title
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Abstract
Official abstract text for this publication.
Provided is a method for manufacturing electronic component improved in chip-holding efficiency, pickup efficiency and contamination resistance in a well-balanced manner, the method comprising a semi-cured adhesive layer-forming step of forming a semi-cured adhesive layer on the rear face of a wafer, a fixing step of fixing the semi-cured adhesive layer of the wafer on a ring frame with a cohesive sheet, a dicing step of dicing the wafer into semiconductor chips, a UV-irradiating step of irradiating ultraviolet ray, and a pick-up step of picking up the chips and semi-cured adhesive layers from the cohesive layer, wherein the cohesive sheet has a cohesive layer of a cohesive agent having a particular composition formed on one face of its base film.
First claim
Opening claim text (preview).
The invention claimed is: 1. A method for manufacturing an electronic component, comprising: (1) a semi-cured adhesive layer-forming step of forming a semi-cured adhesive layer by coating a pasty adhesive on the rear face of a wafer and curing the pasty adhesive partially by UV irradiation or heating into the sheet shape; (2) a fixing step of fixing the semi-cured adhesive layer of the wafer on a ring frame by bonding them to a cohesive sheet; (3) a dicing step of dicing the w…
Assignees
Inventors
Classifications
- H10P72/0442Primary
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
- C09J11/06Primary
Chemistry & Metallurgy · mapped topic
Chemistry & Metallurgy · mapped topic
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Frequently asked questions
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- What does patent US8975347B2 cover?
- Provided is a method for manufacturing electronic component improved in chip-holding efficiency, pickup efficiency and contamination resistance in a well-balanced manner, the method comprising a semi-cured adhesive layer-forming step of forming a semi-cured adhesive layer on the rear face of a wafer, a fixing step of fixing the semi-cured adhesive layer of the wafer on a ring frame with a cohes…
- Who is the assignee on this patent?
- Saito Takeshi, Takatsu Tomomichi, Denki Kagaku Kogyo Kk
- What technology area does this patent fall under?
- Primary CPC classification H10P72/0442. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Mar 10 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).