Transistor-based apparatuses, systems and methods

Patent metadata

Field	Value
Publication number	US-8969924-B2
Application number	US-201313774216-A
Country	US
Kind code	B2
Filing date	Feb 22, 2013
Priority date	May 21, 2012
Publication date	Mar 3, 2015
Grant date	Mar 3, 2015

Abstract

Various aspects of the invention are directed to memory circuits and their implementation. According to an example embodiment, an apparatus includes a channel region between raised source and drain regions which are configured and arranged with respective bandgap offsets relative to the channel region to confine carriers in the channel region. The apparatus also includes front and back gates respectively separated from the channel region by gate dielectrics. The raised source and drain regions have respective portions laterally adjacent the front gate and adjacent the channel region. Carriers are stored in the channel region via application of voltage(s) to the front and back gates, and relative to bias(es) at the source and drain regions.

First claim

What is claimed is:

1. An apparatus comprising:
a front gate;
a channel region below the front gate;
a first gate dielectric between the front gate and the channel region;
a second gate dielectric below the channel region;
a back gate below the channel region and separated from the channel region by the second gate dielectric;
a raised source region having respective portions laterally adjacent the front gate and adjacent the channel region; and
a raised drain region h…

Assignees

• Univ Leland Stanford Junior

Inventors

• Pal Ashish
• Nainani Aneesh
• Saraswat Krishna Chandra

Classifications

• H10D86/215

  Electricity · mapped topic

• H10D86/011

  Electricity · mapped topic

• H10D62/82

  Electricity · mapped topic

• H10D30/023

  Electricity · mapped topic

• H10D30/6757

  Electricity · mapped topic