Efficiency of cycle-reproducible debug processes in a multi-core environment
US-2016378581-A1 · Dec 29, 2016 · US
US8965735B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8965735-B2 |
| Application number | US-80804408-A |
| Country | US |
| Kind code | B2 |
| Filing date | Dec 12, 2008 |
| Priority date | Dec 21, 2007 |
| Publication date | Feb 24, 2015 |
| Grant date | Feb 24, 2015 |
A practical reading order for non-experts. Skip the full description unless you need deep technical detail.
What the patent document calls the invention.
A short plain-language summary of the technical disclosure.
Who owns or filed the patent and who is credited as inventor.
Filing, priority, publication, and grant dates set the timeline.
The legal scope of protection — read this for what is actually claimed.
Technology tags used to group this patent with similar filings.
Prior art links and similar publications in this corpus.
Official abstract text for this publication.
The invention relates to a signal processing device having a first signal processing unit ( 101 ), a second signal processing unit ( 103 ), a third signal processing unit ( 105 ), and a safety unit ( 107 ). The first signal processing unit ( 101 ) and the second signal processing unit ( 103 ) are operable in parallel for providing signal processing redundancy, and are designed to output an output signal in each case in response to an input signal. The safety unit ( 107 ) is designed to replace the first signal processing unit ( 101 ) or the second signal processing unit ( 103 ) with the third signal processing unit ( 105 ).
Opening claim text (preview).
What is claimed is: 1. A signal processing device, comprising: a first signal processing unit; a second signal processing unit; a third signal processing unit, wherein each signal processing unit is designed to output mutually corresponding output signals in response to mutually corresponding input signals; and a safety unit; wherein the first signal processing unit and the second signal processing unit are operable in parallel for providing signal processing redundancy and are interconnectable to form a redundancy block; wherein the first signal processing unit, the second signal processing unit, and the third signal processing unit are connected to the safety unit while the third signal processing unit is in testing; wherein the third signal processing unit, when connected to the safety unit during the testing, is located outside of a safety chain of the first signal processing unit and the second signal processing unit; wherein the safety unit is designed to successively replace in each case the first signal processing unit or the second signal processing unit with the third signal processing unit in order to perform checking of an output response signal of the particular freed-up signal processing unit with respect to a reference value in response to a test input signal according to a predetermined test pattern, wherein the checking uses at least one of i) a test device and ii) a diagnostic device; and wherein the particular freed-up signal processing unit becomes the third signal processing unit and if the output response signal of the third signal processing unit corresponds to the expected response signal for the predetermined test pattern, the functionality of the third signal processing unit is classified as correct and either the first signal processing unit or the second signal processing unit is then replaced with the third signal processing unit. 2. The signal processing device according to claim 1 , wherein the first signal processing unit, the second signal processing unit, and the third signal processing unit are safety-relevant processing channels that have a safety function, and wherein only the first signal processing unit and the second signal processing unit are located in the safety chain and carry out the particular safety function. 3. The signal processing device according to claim 1 , wherein the safety unit comprises a diagnostic device for checking the output signal of the particular signal processing unit in response to a test input signal. 4. The signal processing device according to claim 1 , wherein the first signal processing unit and the second signal processing unit are connected in parallel. 5. The signal processing device according to claim 1 , wherein at least one of the first and the second signal processing unit is designed to monitor the output signal of the second and of the first signal processing unit, respectively. 6. The signal processing device according to claim 1 , further comprising a signal evaluation unit which is designed to output only the output signal of at least one of the first signal processing unit and of the second signal processing unit when the output signals of the first and the second signal evaluation units are at least one of identical to one another and corresponding to one another. 7. The signal processing device according to claim 1 , wherein the safety unit further comprises a switching unit (i) for switching off at least one of the first and the second signal processing unit and (ii) for switching on the third signal processing unit. 8. An integrated signal processing element comprising the signal processing device according to claim 1 . 9. An electronic system, comprising: the signal processing device according to claim 1 ; a signal bus; and an interface unit for supplying the signal bus with the output signal of at least one of the first signal processing unit and the second signal processing unit. 10. A signal processing method implemented using the signal processing device according to claim 1 , the method comprising: processing an input signal by the first signal processing unit and by the second signal processing unit in order to provide signal processing redundancy; replacing the first signal processing unit or the second signal processing unit with the third signal processing unit, using the safety unit; and checking an output response signal of the particular freed-up signal processing unit with respect to a reference value in response to a test input signal according to a predetermined test pattern, using the safety unit, wherein the checking uses at least one of i) a test device and ii) a diagnostic device; and wherein the particular freed-up signal processing unit becomes the third processing unit and if the output response signal of the third signal processing unit corresponds to the expected response signal for the predetermined test pattern, the functionality of the third signal processing unit is classified as correct and either the first signal processing unit or the second signal processing unit is then replaced with the third signal processing unit. 11. A signal processing device, comprising: a first signal processing unit; a second signal processing unit; a third signal processing unit, wherein each signal processing unit is designed to output mutually corresponding output signals in response to mutually corresponding input signals; and a safety unit; wherein the first signal processing unit and the second signal processing unit are connected in parallel for providing signal processing redundancy and are connected to form a redundancy block; wherein the safety unit comprises a diagnostic unit and the third signal processing unit, wherein the diagnostic unit is designed to supply the third signal processing unit with a predetermined test pattern and to evaluate a response signal of the third signal processing unit; wherein the first signal processing unit, the second signal processing unit, and the third signal processing unit are safety-relevant processing channels that have a safety function, and wherein only the first signal processing unit and the second signal processing unit are located in a safety chain and carry out the particular safety function; wherein the first signal processing unit, the second signal processing unit, and the third signal processing unit are connected to the safety unit while the third signal processing unit is in testing; wherein the third signal processing unit, when connected to the safety unit during the testing, is located outside of the safety chain of the first signal processing unit and the second signal processing unit; wherein the safety unit is designed to successively replace in each case the first signal processing unit or the second signal processing unit with the third signal processing unit in order to perform checking of an output response signal of the particular freed-up signal processing unit with respect to a reference value in response to a test input signal according to the predetermined test pattern; and wherein the particular freed-up signal processing unit becomes the third signal processing unit and if the output response signal of the third signal processing unit corresponds to the expected response signal for the predetermined test pattern, the functionality of the third signal processing unit is classified as correct and either the first signal processing unit or the second signal processing unit is then replaced with the tested third signal processing unit as soon as the test is completed. 12. An integrated signal processing element comprising the signal processing device according to claim 11 .
in multi-processor systems, e.g. one processor becoming the primary tester (G06F11/2736 takes precedence) · CPC title
in regular structures · CPC title
Failover techniques · CPC title
with a single idle spare processing component · CPC title
Related publications grouped by family.
Answers are generated from the same data shown on this page.