System and methods for semiconductor device performance prediction during processing

US8962353B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-8962353-B2
Application numberUS-201113234964-A
CountryUS
Kind codeB2
Filing dateSep 16, 2011
Priority dateSep 16, 2011
Publication dateFeb 24, 2015
Grant dateFeb 24, 2015

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Abstract

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Methods and systems for predicting semiconductor device performance criteria during processing. A method is described that includes receiving a semiconductor wafer; performing semiconductor processing on the semiconductor wafer forming active devices that, when completed, will exhibit a device performance criteria; during the semiconductor processing, measuring in line at least one device performance criteria related physical parameter; projecting an estimated value for the device performance criteria of the active devices using the at least one in line measurement and using estimated measurements for device performance criteria related physical parameters corresponding to later semiconductor processing steps; comparing the estimated value for the device performance criteria to an acceptable range; and determining, based on the comparing, whether the active devices on the semiconductor wafer will have a device performance criteria within the acceptable range. A system for processing semiconductor wafers that includes a programmable processor for performing the methods is described.

First claim

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What is claimed is: 1. A method, comprising: receiving a semiconductor wafer for semiconductor processing to form active devices thereon; performing semiconductor processing on the semiconductor wafer forming active devices that, when completed, will exhibit a device performance criteria; during the semiconductor processing and prior to completing the forming the active devices on the semiconductor wafer, measuring in line at least one physical parameter of the active devices,…

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What does patent US8962353B2 cover?
Methods and systems for predicting semiconductor device performance criteria during processing. A method is described that includes receiving a semiconductor wafer; performing semiconductor processing on the semiconductor wafer forming active devices that, when completed, will exhibit a device performance criteria; during the semiconductor processing, measuring in line at least one device perfo…
Who is the assignee on this patent?
Wang Jen-Pan, Chen Chao-Chi, Huang Yaling, and 1 more
What technology area does this patent fall under?
Primary CPC classification H10P74/23. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Feb 24 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).